llvm-svn: 179648

llvm-svn: 179647

llvm-svn: 179646

llvm-svn: 179645

llvm-svn: 179622

llvm-svn: 179611

llvm-svn: 179610

llvm-svn: 179607

llvm-svn: 179601

llvm-svn: 179593

llvm-svn: 179591

LLVMGetThreadLocalMode - exposes GlobalVariable::getThreadLocalMode
LLVMSetThreadLocalMode - exposes GlobalVariable::setThreadLocalMode
LLVMIsExternallyInitialized - exposes GlobalVariable::isExternallyInitialized
LLVMSetExternallyInitialized - exposes GlobalVariable::setExternallyInitialized
LLVMThreadLocalMode - maps to GlobalVariable::ThreadLocalMode

Patch by Moritz Maxeiner!

llvm-svn: 179588

If a switch instruction has a case for every possible value of its type,
with the same successor, SimplifyCFG would replace it with an icmp ult,
but the computation of the bound overflows in that case, which inverts
the test.

Patch by Jed Davis!

llvm-svn: 179587

llvm-svn: 179582

These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.

rdar://13638090

llvm-svn: 179575

Two return types are not equivalent if one is a pointer and the other is an
integral. This is because we cannot bitcast a pointer to an integral value.
PR15185

llvm-svn: 179569

This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic
llvm-svn: 179567

SLPVectorizer: Make it a function pass and add code for hoisting the vector-gather sequence out of loops.

llvm-svn: 179562

Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546

llvm-svn: 179545

llvm-svn: 179544

llvm-svn: 179542

I will remove the isBigEndianHost function once I update clang.

The ifdef logic is designed to
* not use configure/cmake to avoid breaking -arch i686 -arch ppc.
* default to little endian
* be as small as possible

It looks like sys/endian.h is the preferred header on most modern BSD systems,
but it is better to change this in a followup patch as machine/endian.h is
available on FreeBSD, OpenBSD, NetBSD and OS X.

llvm-svn: 179527

This is a rework of the broken parts in r179373 which were subsequently reverted in r179374 due to incompatibility with C++98 compilers.  This version should be ok under C++98.

llvm-svn: 179520

Add an option -vectorize-slp-aggressive for running the BB vectorizer. Make -fslp-vectorize run the slp-vectorizer.

llvm-svn: 179508

llvm-svn: 179505

llvm-svn: 179504

Now that the CR spilling issues have been resolved, we can remove the
unmodeled-side-effect attributes from the comparison instructions (and also
mark them as isCompare). By allowing these, by default, to have unmodeled side
effects, we were hiding problems with CR spilling; but everything seems much
happier now.

llvm-svn: 179502

This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition
registers, the spill location is specified relative to the stack pointer (SP +
8). However, this is not relative to the SP after the new stack frame is
established, but instead relative to the caller's stack pointer (it is stored
into the linkage area of the parent's stack frame).

So, like with the link register, we don't directly spill the CRs with other
callee-saved registers, but just mark them to be spilled during prologue
generation.

In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32).

llvm-svn: 179500

llvm-svn: 179494

One performs: (X == 13 | X == 14) -> X-13 <u 2
The other: (A == C1 || A == C2) -> (A & ~(C1 ^ C2)) == C1

The problem is that there are certain values of C1 and C2 that
trigger both transforms but the first one blocks out the second,
this generates suboptimal code.

Reordering the transforms should be better in every case and
allows us to do interesting stuff like turn:
  %shr = lshr i32 %X, 4
  %and = and i32 %shr, 15
  %add = add i32 %and, -14
  %tobool = icmp ne i32 %add, 0

into:
  %and = and i32 %X, 240
  %tobool = icmp ne i32 %and, 224

llvm-svn: 179493

llvm-svn: 179483

llvm-svn: 179479

llvm-svn: 179478

Test case by llvm-stress.

llvm-svn: 179477

SLPVectorizer: Add support for trees that don't start at binary operators, and add the cost of extracting values from the roots of the tree.

llvm-svn: 179475

For when 16 TB just isn't enough.

llvm-svn: 179474

This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.

llvm-svn: 179473

64-bit code models need multiple relocations that can't be inferred from
the opcode like they can in 32-bit code.

llvm-svn: 179472

Constant pool entries are accessed exactly the same way as global
variables.

llvm-svn: 179471