The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like the other EH passes.

llvm-svn: 182321

AsmPrinter::EmitLinkage() does not handle dllimport linkage.  The LLVM
verifier should also be fixed to reject this.

llvm-svn: 182320

llvm-svn: 182317

protocols that declare the same property of incompatible
types, issue a warning when class implementation synthesizes 
the property. // rdar://13075400

llvm-svn: 182316

llvm-svn: 182315

As discussed, LoopUtils.h is a better name.

llvm-svn: 182314

llvm-svn: 182310

llvm-svn: 182309

llvm-svn: 182308

llvm-svn: 182307

By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306

llvm-svn: 182305

GetPageSize wraps sysconf(_SC_PAGESIZE) on POSIX platforms, but
sysconf resides in libc.  To make this libc-independent on Linux,
move the wrapper to sanitizer_mac.cc and return the Linux-specific
constant EXEC_PAGESIZE in the sanitizer_linux.cc implementation.

llvm-svn: 182303

llvm-svn: 182302

llvm-svn: 182301

Now that the preheader insertion logic in LoopSimplify is externally exposed,
use it, and remove the copy-and-pasted version.

No functionality change intended.

llvm-svn: 182300

Other passes, PPC counter-loop formation for example, also need to add loop
preheaders outside of the regular loop simplification pass. This makes
InsertPreheaderForLoop a global function so that it can be used by other
passes.

No functionality change intended.

llvm-svn: 182299

[NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter.  This was causing a symbol name error in the output PTX.

llvm-svn: 182298

llvm-svn: 182297

As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.

No functionality change intended.

llvm-svn: 182296

When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.

In short, this is to help us sleep better at night.

llvm-svn: 182295

llvm-svn: 182294

R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

llvm-svn: 182293

llvm-svn: 182292

The -debug-only option is only available on asserts builds.

llvm-svn: 182291

llvm-svn: 182290

This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286

The hardware supports rotr and not rotl.

llvm-svn: 182285

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284

This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282

VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

llvm-svn: 182281

llvm-svn: 182280

Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

llvm-svn: 182279

llvm-svn: 182278

__libc_stack_end is made into a weak symbol if possible.  If libc is
not linked, read args and environment from /proc.

llvm-svn: 182276

Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.

llvm-svn: 182274

llvm-svn: 182272