Commits · ee787a7665712396311a51675bf0223e80c4c745 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Jan 10, 2017
- Make the test accept different OpCode values since it doesn't really care about the value. · ee787a76
  Douglas Yung authored Jan 10, 2017
  ee787a76
- DAG: Avoid OOB when legalizing vector indexing · 0b382a7c
  Matt Arsenault authored Jan 10, 2017
  0b382a7c
- [WebAssembly] Only RAUW a constant once in FixFunctionBitcasts · 7acb42a4
  Derek Schuff authored Jan 10, 2017
  7acb42a4
- AMDGPU: Add tests for HasMultipleConditionRegisters · 8871683d
  Matt Arsenault authored Jan 10, 2017
  8871683d
- [X86][AVX512]Improving shuffle lowering by using AVX-512 EXPAND* instructions · bcd03e7f
  Michael Zuckerman authored Jan 10, 2017
  bcd03e7f
- [AArch64] Add support for lowering bitreverse to the rbit instruction. · 3daffbf6
  Chad Rosier authored Jan 10, 2017
  3daffbf6
- [mips] Fix Mips MSA instrinsics · 548a53f5
  Simon Dardis authored Jan 10, 2017
  548a53f5
- [mips] Honour -mno-odd-spreg for vector splat (again) · 0e9e2373
  Simon Dardis authored Jan 10, 2017
  0e9e2373
- AMD family 17h (znver1) enablement · d55b8312
  Craig Topper authored Jan 10, 2017
  d55b8312
Jan 09, 2017
- [X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests · fa328947
  Simon Pilgrim authored Jan 09, 2017
  fa328947
- PeepholeOptimizer: Do not replace SubregToReg(bitcast like) · ba7d95d4
  Matthias Braun authored Jan 09, 2017
  ba7d95d4
- Revert r291092 because it introduces a crash. · 1559e886
  Michael Kuperstein authored Jan 09, 2017
  1559e886
- X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB. · d497d360
  Vyacheslav Klochkov authored Jan 09, 2017
  d497d360
- AMDGPU: Add Assert[SZ]Ext during argument load creation · 6dca542b
  Matt Arsenault authored Jan 09, 2017
  6dca542b
- [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern. · 0f23b2ba
  Simon Pilgrim authored Jan 09, 2017
  0f23b2ba
- [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate pattern. · d990cd37
  Simon Pilgrim authored Jan 09, 2017
  d990cd37
- [X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests · f8538572
  Simon Pilgrim authored Jan 09, 2017
  f8538572
- [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486. · b14afd45
  Bjorn Pettersson authored Jan 09, 2017
  b14afd45
- [AVX-512] Change another pattern that was using BLENDM to use masked moves. A... · 96ab6fd2
  Craig Topper authored Jan 09, 2017
  96ab6fd2
- [AVX-512] Add patterns to use a zero masked VPTERNLOG instruction for vselects... · 6393afce
  Craig Topper authored Jan 09, 2017
  6393afce
Jan 08, 2017
- [AVX-512] If avx512dq is available use vpmovm2d/vpmovm2q instead of vselect of... · f51ba1e3
  Craig Topper authored Jan 08, 2017
  f51ba1e3
- [X86] Add avx512bw and avx512dq command lines to the vector compare results test. · 0930a523
  Craig Topper authored Jan 08, 2017
  0930a523
- [x86] fix usage of stale operands when lowering select · bf51c8a9
  Sanjay Patel authored Jan 08, 2017
  bf51c8a9
- [AVR] Implement TargetLoweing::getRegisterByName · 8fa6d8db
  Dylan McKay authored Jan 07, 2017
  8fa6d8db
Jan 07, 2017
- [AVX-512] Remove patterns from the other VBLENDM instructions. They are all... · a74e3088
  Craig Topper authored Jan 07, 2017
  a74e3088
- [X86] Regenerate a test to remove tab characters. · 2d02d492
  Craig Topper authored Jan 07, 2017
  2d02d492
- [AVX-512] Add masked forms of the alternate MOVDDUP patterns. · da84ff3e
  Craig Topper authored Jan 07, 2017
  da84ff3e
- [X86][AVX2] Regenerate arithmetic tests · 935beac1
  Simon Pilgrim authored Jan 07, 2017
  935beac1
- [X86][AVX512] Use lowerShuffleAsRepeatedMaskAndLanePermute for non-VBMI v64i8 shuffles (PR31470) · a1b8e2c7
  Simon Pilgrim authored Jan 07, 2017
  a1b8e2c7
- [WebAssembly] Don't abort on code with UB. · 0e2ceb81
  Dan Gohman authored Jan 07, 2017
  0e2ceb81
- [WebAssembly] Add a pass to create wrappers for function bitcasts. · 1b637458
  Dan Gohman authored Jan 07, 2017
  1b637458
Jan 06, 2017
- AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodes · 06200bd7
  Jan Vesely authored Jan 06, 2017
  06200bd7
- [X86][SSE] Standardized triples in vector shift tests · 08519d7b
  Simon Pilgrim authored Jan 06, 2017
  08519d7b
- AArch64CollectLOH: Rewrite as block-local analysis. · 258b847c
  Matthias Braun authored Jan 06, 2017
  258b847c
- [AMDGPU] Do not emit .AMDGPU.config section for amdhsa · 67a6d540
  Konstantin Zhuravlyov authored Jan 06, 2017
  67a6d540
- [X86][AVX] Regenerate shuffle 128-bit tests. · 9122793b
  Simon Pilgrim authored Jan 06, 2017
  9122793b
- [X86][AVX] Regenerate tzcnt tests. · 10cc5d55
  Simon Pilgrim authored Jan 06, 2017
  10cc5d55
- [AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. · e86fb932
  Craig Topper authored Jan 06, 2017
  e86fb932
- [AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. · 8cbac879
  Craig Topper authored Jan 06, 2017
  8cbac879
- [SelectionDAG] Correctly transform range metadata to AssertZExt · eaba06cf
  David Majnemer authored Jan 06, 2017
  eaba06cf