llvm-svn: 31884

llvm-svn: 31882

features autodetected.  This fixes PR1010 and Regression/CodeGen/X86/xmm-r64.ll
on non-x86-64 hosts.

llvm-svn: 31879

llvm-svn: 31874

Also, valist should create a pointer RC reg class value, not a GPRC value.

llvm-svn: 31840

llvm-svn: 31839

llvm-svn: 31838

The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model.  This fixes assembler errors when compiling 403.gcc with
tail merging enabled.

Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion.  Only if branches need expansion are instructions rewritten
and created.  This should make branch select faster, and eliminates the
Bxx instructions from the .td file.

llvm-svn: 31837

issues to the ground.

llvm-svn: 31836

value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835

llvm-svn: 31834

llvm-svn: 31833

clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.

llvm-svn: 31832

llvm-svn: 31830

llvm-svn: 31828

2. Offsets on 64-bit stores are still in bytes.

llvm-svn: 31824

llvm-svn: 31823

llvm-svn: 31813

llvm-svn: 31805

llvm-svn: 31799

llvm-svn: 31797

Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.

llvm-svn: 31795

llvm-svn: 31794

This is a general clean up of the PowerPC ABI.  Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792

before printing it.

llvm-svn: 31791

llvm-svn: 31790

llvm-svn: 31785

llvm-svn: 31778

llvm-svn: 31776

llvm-svn: 31775

llvm-svn: 31774

llvm-svn: 31771

Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).

llvm-svn: 31770

llvm-svn: 31768

llvm-svn: 31765

llvm-svn: 31764

llvm-svn: 31763

addrmodes.

llvm-svn: 31757

CBE and interpreter.

llvm-svn: 31755

llvm-svn: 31754