llvm-svn: 117069

llvm-svn: 117067

llvm-svn: 117064

llvm-svn: 117059

llvm-svn: 117047

llvm-svn: 117040

llvm-svn: 117039

llvm-svn: 117002

llvm-svn: 116992

llvm-svn: 116981

extension register.

llvm-svn: 116970

registers.

llvm-svn: 116961

llvm-svn: 116588

llvm-svn: 116540

are just forms of that instruction).

llvm-svn: 116538

llvm-svn: 116498

here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471

llvm-svn: 116466

- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464

llvm-svn: 116431

llvm-svn: 116421

llvm-svn: 116412

just yet.

llvm-svn: 116386

llvm-svn: 116385

arithmetic-with-carry-in instructions.

llvm-svn: 116384

llvm-svn: 116383

llvm-svn: 116379

llvm-svn: 116375

llvm-svn: 116370

llvm-svn: 116365

Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359

llvm-svn: 116354

llvm-svn: 116348

ARM instructions.

llvm-svn: 116313

register operand.

llvm-svn: 116259

concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112

llvm-svn: 116024

llvm-svn: 115414