llvm-svn: 143895

llvm-svn: 143782

llvm-svn: 143781

llvm-svn: 143745

llvm-svn: 143744

llvm-svn: 143714

llvm-svn: 143673

llvm-svn: 143661

utils: Remove (way) old nightly test scripts, I don't think anyone uses them and LNT has way better tools than this.

llvm-svn: 143655

 - llvm-build should now be Python2.4 compatible as best I know.

llvm-svn: 143641

llvm-svn: 143634

header.

llvm-svn: 143629

dependency table used by llvm-config.

llvm-svn: 143628

 - Useful for migrating or auto-upgrading the format schema.

llvm-svn: 143626

llvm-svn: 143625

llvm-svn: 143624

llvm-build: Validate information on the loaded components and form the topological ordering among them (as well as validating that there are no cycles).
 - Currently we require that all references between components (except the parent relation) fit into a DAG -- this could be relaxed later if it ever proves to be useful.

llvm-svn: 143623

differentiate between strings and lists.

llvm-svn: 143622

llvm-svn: 143621

llvm-svn: 143620

one aspect of them by having them use the (annoying, if not broken)
proper library dependency model for adding the LLVMTableGen library as
a dependency. This could manifest as a link order issue in the presence
of separate LLVM / Clang source builds with CMake and a linker that
really cares about such things.

Also, add the Support dependency to llvm-tblgen itself so that it
doesn't rely on TableGen's transitive Support dependency. A parallel
change for clang-tblgen will be forthcoming.

llvm-svn: 143531

llvm-svn: 143525

Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts...

llvm-svn: 143302

For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

llvm-svn: 143233

If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

llvm-svn: 143200

llvm-svn: 143164

llvm-svn: 143153

 - Also, cleanup site.exp files in example tests.

llvm-svn: 143141

llvm-svn: 142880

llvm-svn: 142878

rdar://9683410

llvm-svn: 142856

llvm-svn: 142764

llvm-svn: 142763

llvm-svn: 142741

llvm-svn: 142726

llvm-svn: 142691

llvm-svn: 142682

llvm-svn: 142675

Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670

llvm-svn: 142647