llvm-svn: 133821

- Rename TargetRegisterDesc to MCRegisterDesc.

llvm-svn: 133820

The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

llvm-svn: 133818

llvm-svn: 133815

The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates.

llvm-svn: 133814

instructions can be used to match combinations of multiply/divide and VCVT 
(between floating-point and integer, Advanced SIMD).  Basically the VCVT 
immediate operand that specifies the number of fraction bits corresponds to a 
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a 
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a 
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3

llvm-svn: 133813

     .file and .loc directives.

Ideally, we would utilize the existing support in AsmPrinter for this, but
I cannot find a way to get .file and .loc directives to print without the
rest of the associated DWARF sections, which ptxas cannot handle.

llvm-svn: 133812

 enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811

rdar://9667872

llvm-svn: 133808

static variables or functions. 

llvm-svn: 133803

     targets: g80, gt200, gf100(fermi)

llvm-svn: 133799

llvm-svn: 133798

we cannot duplicate to every predecessor.

llvm-svn: 133797

llvm-svn: 133793

llvm-svn: 133792

Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.

This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

llvm-svn: 133791

llvm-svn: 133787

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

llvm-svn: 133776

llvm-svn: 133770

llvm-svn: 133767

llvm-svn: 133766

llvm-svn: 133759

llvm-svn: 133756

llvm-svn: 133741

llvm-svn: 133739

llvm-svn: 133738

     parameters if SM >= 2.0

- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
  registers

llvm-svn: 133736

llvm-svn: 133735

llvm-svn: 133734

     st.param and ld.param

FIXME: Test cases still need to be updated
llvm-svn: 133733

FIXME: DCE is eliminating the final st.param.x calls, figure out why
llvm-svn: 133732

llvm-svn: 133729

llvm-svn: 133726

llvm-svn: 133725

This reverts commit e8e00f5efb4a22238f2407bf813de4606f30c5aa.

The cmake build on OS X is still broken.

llvm-svn: 133718

llvm-svn: 133717

It broke the build worse.

llvm-svn: 133716

llvm-svn: 133714

It has only one user. This eliminates the last include of
config.h from the public headers -- ideally, config.h
shouldn't even be installed by `make install` anymore.

llvm-svn: 133713