Separate AVXCC and SSECC printing for cmpps/pd/ss/sd and add masking before the switch statement. This keeps the unreachable default case from being hit if the instruction was created with an intrinsic with too large of an immediate.

llvm-svn: 165483

In parseMSRMaskOperand, add an explicit check for the operand being an identifier instead of just having an assert.

llvm-svn: 165480

Remove some dead code from ARMAsmPrinter. Add virtual and LLVM_OVERRIDE to the other methods. Mark some of the helper methods as private.

llvm-svn: 165479

Remove some unused code in the X86AsmPrinter. Add LLVM_OVERRIDE and virtual keywords to the remaining interface methods.

llvm-svn: 165478

llvm-svn: 165467

Vector compare using altivec 'vcmpxxx' instructions have as third argument
a vector register instead of CR one, different from integer and float-point
compares. This leads to a failure in code generation, where 'SelectSETCC'
expects a DAG with a CR register and gets vector register instead.

This patch changes the behavior by just returning a DAG with the 
vector compare instruction based on the type. The patch also adds a testcase
for all vector types llvm defines.

It also included a fix on signed 5-bits predicates printing, where
signed values were not handled correctly as signed (char are unsigned by
default for PowerPC). This generates 'vspltisw' (vector splat)
instruction with SIM out of range.

llvm-svn: 165419

llvm-svn: 165418

llvm-svn: 165411

This patch add altivec support for v4i32 to v4f32 and for v4f32 to
v4i32 vector rounding conversion.

llvm-svn: 165409

llvm-svn: 165402

Otherwise it will try to use SSE patterns and fail horribly if sse is disabled.
Fixes PR14035.

llvm-svn: 165377

move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351

Contributer: Vladimir Medic
llvm-svn: 165350

Contributer: Vladimir Medic
llvm-svn: 165346

into separate versions for the Darwin and 64-bit SVR4 ABIs.  This will
facilitate doing more major surgery on the 64-bit SVR4 ABI in the near future.

llvm-svn: 165336

llvm-svn: 165324

llvm-svn: 165322

llvm-svn: 165320

Implement TargetData with the DataLayout class, this will allow LLVM projects to transition to DataLayout without loosing functionality.

llvm-svn: 165318

- Mark the BCC and BLR defs as isCodeGenOnly per error output from
llvm-tblgen -gen-asm-matcher.

 PPCInstrInfo.td |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

llvm-svn: 165315

llvm-svn: 165303

Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos and mark them as pseudos in the td file.

llvm-svn: 165302

Follow up to r165072. Try a different approach: only move the load when it's going to be folded into the call. rdar://12437604

llvm-svn: 165287

segmented registers.  Test case to come.

llvm-svn: 165275

a pointer to a type, in order to remove the uses of getGlobalContext().

Patch by Tyler Nowicki.

llvm-svn: 165255

Make sure functions located in user specified text sections (via the
section attribute) are located together with the default text sections.
Otherwise, for large object files, the relocations for call instructions
are more likely to be out of range. This becomes even more likely in the
presence of LTO.

rdar://12402636

llvm-svn: 165254

a) frame setup instructions define the prologue
b) we shouldn't change our location mid-stream

Add a test to make sure that the stack adjustment stays within
the prologue.

llvm-svn: 165250

- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
  retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.

llvm-svn: 165241

- add tokens to PPCInstrInfo.td and PPCInstr64Bit.td to resolve
"Instruction 'foo' has no tokens" errors during llvm-tblgen
-gen-asm-matcher attempts.  At this time, the added
tokens are "#comment" style rather than the actual mnemonic.  This will
be revisited once the rest of the base asmparser bits get straightened
out for ppc64-elf-linux.

llvm-svn: 165237

llvm-svn: 165233

llvm-svn: 165205

macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199

This patch is a partial implementation of mips .set assembler directive. Directive is defined as follows:
.set option
The patch implements following options

    at - lets the assembler use the $at register for macros,
         but generates warnings if the source program uses $at

    noat - let source programs use $at without issuingwarnings.

    noreorder - prevents the assembler from reordering machine 
                language instructions.
    nomacro - causes the assembler to print a warning whenever 
              an assembler operation generates more than one 
              machine language instruction.
    macro - lets the assembler generate multiple machine instructions 
            from a single assembler instruction
    reorder - lets the assembler reorder machine language 
               instructions to improve performance

The above variants are parsed and their boolean values set or unset.
The code to actually use them will come later.

Following options are not implemented yet:

nomips16
nomicromips
move
nomove

Contributer: Vladimir Medic
llvm-svn: 165194

llvm-svn: 165182

in the Intel syntax.

The MC layer supports emitting in the Intel syntax, but this would require the
inline assembly MachineInstr to be lowered to an MCInst before emission.  This
is potential future work, but for now emitting directly from the MachineInstr
suffices.

llvm-svn: 165173

for the number of bytes in a particular instruction
to using
   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
   Desc.getSize()

This is necessary with the advent of 16 bit instructions with
mips16 and micromips. It is also puts Mips in compliance with
the other targets for getting instruction size.

llvm-svn: 165171

llvm-svn: 165141

enums. This allows for better encapsulation of the Attributes class.

llvm-svn: 165132

Corrects a problem whereby MCSchedModel was not being set up when
the CPU type was auto-detected.

Patch by Andy Zhang.

llvm-svn: 165122

more detail.

llvm-svn: 165099