- Jan 15, 2013
-
-
Jack Carter authored
we need to generate a N64 compound relocation R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE. The bug was exposed by the SingleSourcetest case DuffsDevice.c. Contributer: Jack Carter llvm-svn: 172496
-
- Jan 14, 2013
-
-
Dmitri Gribenko authored
llvm-svn: 172481
-
David Greene authored
Fix a casting-away-const compiler warning. llvm-svn: 172471
-
- Jan 12, 2013
-
-
NAKAMURA Takumi authored
MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function] llvm-svn: 172319
-
NAKAMURA Takumi authored
llvm-svn: 172315
-
Jack Carter authored
register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
-
- Jan 08, 2013
-
-
Jack Carter authored
an R_MIPS_GPREL16 relocation. Contributer: Jack Carter llvm-svn: 171882
-
Jack Carter authored
value in the 64 bit .eh_frame section. It doesn't however allow exception handling to work yet since it depends on the correct relocation model being set in the ELF header flags. Contributer: Jack Carter llvm-svn: 171881
-
Eli Bendersky authored
No change in functionality. llvm-svn: 171822
-
- Jan 07, 2013
-
-
Jordan Rose authored
This is necessary not only for representing empty ranges, but for handling multibyte characters in the input. (If the end pointer in a range refers to a multibyte character, should it point to the beginning or the end of the character in a char array?) Some of the code in the asm parsers was already assuming this anyway. llvm-svn: 171765
-
Craig Topper authored
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. llvm-svn: 171697
-
Chandler Carruth authored
a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
-
- Jan 05, 2013
-
-
Akira Hatanaka authored
and add stack alignment information. llvm-svn: 171587
-
- Jan 04, 2013
-
-
Akira Hatanaka authored
vectors are being compared. llvm-svn: 171517
-
Akira Hatanaka authored
llvm-svn: 171515
-
Akira Hatanaka authored
shift_rotate_imm64. llvm-svn: 171513
-
Akira Hatanaka authored
llvm-svn: 171511
-
Akira Hatanaka authored
llvm-svn: 171510
-
- Jan 02, 2013
-
-
Chandler Carruth authored
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
-
Chandler Carruth authored
utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
-
- Dec 22, 2012
-
-
Akira Hatanaka authored
instructions. llvm-svn: 170956
-
Akira Hatanaka authored
llvm-svn: 170955
-
Akira Hatanaka authored
llvm-svn: 170954
-
Akira Hatanaka authored
was not catching the error. llvm-svn: 170953
-
Akira Hatanaka authored
llvm-svn: 170952
-
Akira Hatanaka authored
instructions. llvm-svn: 170950
-
- Dec 21, 2012
-
-
Akira Hatanaka authored
llvm-svn: 170948
-
Akira Hatanaka authored
llvm-svn: 170947
-
Akira Hatanaka authored
llvm-svn: 170944
-
Akira Hatanaka authored
llvm-svn: 170942
-
Akira Hatanaka authored
llvm-svn: 170940
-
Akira Hatanaka authored
llvm-svn: 170939
-
Akira Hatanaka authored
llvm-svn: 170937
-
Akira Hatanaka authored
llvm-svn: 170936
-
Reed Kotler authored
llvm-svn: 170822
-
- Dec 20, 2012
-
-
Reed Kotler authored
next few days but it's already tested a lot from test-suite and works fine. This patch completes almost 100% pass of test-suite for mips 16. llvm-svn: 170674
-
Reed Kotler authored
on code that has large frames which will not yet compile correctly. llvm-svn: 170673
-
Reed Kotler authored
llvm-svn: 170669
-
Reed Kotler authored
llvm-svn: 170667
-
Reed Kotler authored
We use an unused Mips 32 register for the emergency slot instead of using the stack. llvm-svn: 170665
-