VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.

llvm-svn: 127647

llvm-svn: 119050

weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084

llvm-svn: 115580

disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.

llvm-svn: 108226

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

llvm-svn: 101642

for the encoding and is not the same as vmptrld.

llvm-svn: 97992

llvm-svn: 96076

fix swapgs to be spelled right.

llvm-svn: 96058

llvm-svn: 96045

llvm-svn: 91900

data on them, for example:

	addb	%al, (%rax)
simple-tests.txt:11:5: error: excess data detected in input
0 0 0 0 0 
    ^

llvm-svn: 91896

comments.  Also, check in a simple testcase for the disassembler,
including a test for r91864

llvm-svn: 91894