CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.

llvm-svn: 106701

llvm-svn: 106699

Do not use "ValueMap" as a name for a local variable or an argument.

llvm-svn: 106698

llvm-svn: 106697

void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.

llvm-svn: 106693

llvm-svn: 106692

llvm-svn: 106686

llvm-svn: 106685

llvm-svn: 106683

Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction

llvm-svn: 106678

llvm-svn: 106677

llvm-svn: 106672

llvm-svn: 106671

branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.

llvm-svn: 106662

into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.

llvm-svn: 106643

Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.

llvm-svn: 106634

to using that.

llvm-svn: 106633

MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

llvm-svn: 106631

atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.

llvm-svn: 106630

llvm-svn: 106627

llvm-svn: 106626

llvm-svn: 106623

llvm-svn: 106622

llvm-svn: 106621

Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.

Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614

Thanks Daniel!

llvm-svn: 106608

Replace ScalarEvolution's private copy of getLoopPredecessor
with LoopInfo's public copy.

llvm-svn: 106603

llvm-svn: 106600

llvm-svn: 106598

is another max which folds. This fixes PR7454.

llvm-svn: 106594

testcases this time.

llvm-svn: 106593

If a metadata operand is seeded in value map and the metadata should also be seeded in value map. This is not limited to function local metadata. 

Failure to seed metdata in such cases causes troubles when in a cloned module, metadata from a new module refers to values in old module. Usually this results in mysterious bugpoint crashes. For example,

 Checking to see if we can delete global inits: Unknown constant!
 UNREACHABLE executed at /d/g/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:904!

llvm-svn: 106592

llvm-svn: 106591

llvm-svn: 106588

llvm-svn: 106586

instructions.

This does not affect codegen much because SUBREG_TO_REG is only used by X86 and
X86 does not use the register scavenger, but it prevents verifier errors.

llvm-svn: 106583

Radar 8031193.

llvm-svn: 106582

llvm-svn: 106576

llvm-svn: 106574

llvm-svn: 106573