llvm-svn: 41159

fixed to generate instructions (add, lui) glued!

llvm-svn: 41158

Newline added after macros at function init on generated asm!

llvm-svn: 41157

llvm-svn: 41156

llvm-svn: 41155

llvm-svn: 41154

Added InsertNoop support

llvm-svn: 41153

MipsAdd opcode added

llvm-svn: 41152

Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151

llvm-svn: 41150

llvm-svn: 41149

hard to catch bugs with retaddr lowering

llvm-svn: 41104

llvm-svn: 41103

llvm-svn: 41059

see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049

llvm-svn: 41048

llvm-svn: 41021

able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020

Make a 'memop' pattern just for them.

llvm-svn: 41017

llvm-svn: 41013

Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).

llvm-svn: 41010

llvm-svn: 41009

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

llvm-svn: 40986

llvm-svn: 40985

llvm-svn: 40982

llvm-svn: 40973

divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.

llvm-svn: 40972

GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.

llvm-svn: 40970

(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958

llvm-svn: 40957

llvm-svn: 40908

SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906

llvm-svn: 40887

Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886

llvm-svn: 40881

llvm-svn: 40878

(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877

llvm-svn: 40868

llvm-svn: 40854