llvm-svn: 41159

fixed to generate instructions (add, lui) glued!

llvm-svn: 41158

Newline added after macros at function init on generated asm!

llvm-svn: 41157

llvm-svn: 41156

llvm-svn: 41155

llvm-svn: 41154

Added InsertNoop support

llvm-svn: 41153

MipsAdd opcode added

llvm-svn: 41152

Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151

llvm-svn: 41150

llvm-svn: 41149

llvm-svn: 40757

still under discussion.

llvm-svn: 40549

AsmPrinter::doFinalization.

llvm-svn: 40487

llvm-svn: 40132

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764

Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763

llvm-svn: 39761

FI's created the write way to represent Mips stack

llvm-svn: 39760

llvm-svn: 39759

llvm-svn: 39758

llvm-svn: 39737

zero if they see a target triple they don't understand.

llvm-svn: 38463

- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461