llvm-svn: 45859

llvm-svn: 45854

llvm-svn: 45852

- Cleaned up custom load/store logic, common code is now shared [see note
  below], cleaned up address modes

- More test cases: various intrinsics, structure element access (load/store
  test), updated target data strings, indirect function calls.

Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode
structures: they now share a common base class, LSBaseSDNode, that
provides an interface to their common functionality. There is some hackery
to access the proper operand depending on the derived class; otherwise,
to do a proper job would require finding and rearranging the SDOperands
sent to StoreSDNode's constructor. The current refactor errs on the
side of being conservatively and backwardly compatible while providing
functionality that reduces redundant code for targets where loads and
stores are custom-lowered.

llvm-svn: 45851

llvm-svn: 45849

Cosmetic changes to spacing to match gcc (some dejagnu
tests actually care).

llvm-svn: 45848

both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843

llvm-svn: 45838

llvm-svn: 45837

Likewise fix up a bunch of other libcalls.  While
there I remove NEG_F32 and NEG_F64 since they are
not used anywhere.  This fixes 9 Ada ACATS failures.

llvm-svn: 45833

x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829

llvm-svn: 45826

llvm-svn: 45825

inferred from the instr patterns.

llvm-svn: 45824

llvm-svn: 45821

instructions (with patterns) that load memory marked, for example.

llvm-svn: 45818

or being side-effect free.

llvm-svn: 45816

llvm-svn: 45813

because assembler/linker can't cope with weak absolutes.
PR 1880.

llvm-svn: 45811

Do not use the stack pointer directly, issue a copyfromreg instead. Otherwise we can end up with something like ADD32ri %esp, x which two-address pass won't like.

llvm-svn: 45798

than hardware supported type will be scalarized, so we
can infer their alignment from that info.

We now codegen pr1845 into:

_boolVectorSelect:
	lbz r2, 0(r3)
	stb r2, -16(r1)
	blr 

llvm-svn: 45796

llvm-svn: 45792

llvm-svn: 45768

llvm-svn: 45766

on 64-bit builds.  Analysis and original patch
by Török Edwin.  Code audit found another place
with the same problem, also fixed here.

llvm-svn: 45746

the code generated is not wonderful.  This turns a miscompilation into
a code quality bug (noted in the ppc readme).  This fixes PR642, which
is over 2 years old (!).  Nate, please review this.

llvm-svn: 45742

llvm-svn: 45734

llvm-svn: 45733

llvm-svn: 45731

llvm-svn: 45727

llvm-svn: 45726

llvm-svn: 45725

llvm-svn: 45723

llvm-svn: 45720

llvm-svn: 45712

llvm-svn: 45703

llvm-svn: 45701

llvm-svn: 45699

llvm-svn: 45698

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695