Fixes rdar://8017638

llvm-svn: 104617

This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615

The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

llvm-svn: 104611

llvm-svn: 104571

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

llvm-svn: 104552

llvm-svn: 104549

Use the tablegen-produced enums.

llvm-svn: 104493

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492

MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
  addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453

llvm-svn: 104452

llvm-svn: 104435

llvm-svn: 104421

llvm-svn: 104394

that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377

llvm-svn: 104337

Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336

pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333

llvm-svn: 104331

llvm-svn: 104330

eliminating the gymnastics around the ContainsFPCode var.

llvm-svn: 104328

llvm-svn: 104326

isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318

differently. This will make adding ELF support easier in the long run.

llvm-svn: 104317

tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308

llvm-svn: 104275

llvm-svn: 104272

llvm-svn: 104271

have a pattern and it had an invalid encoding.

llvm-svn: 104244

instructions.

llvm-svn: 104231

16-bit and 32-bit pushf and popf.

llvm-svn: 104228

llvm-svn: 104204

doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203

Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.

llvm-svn: 104147

llvm-svn: 104122

prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120

CALL64pcrel32, for the same reason.

llvm-svn: 104116

llvm-svn: 104112

avoid same prefix byte problem as in r104062.

llvm-svn: 104108

opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.

llvm-svn: 104091