are not yet updated properly, but that's a separate
task.

llvm-svn: 55187

llvm-svn: 55186

handled correctly, and change a few SmallVector uses to use
size 0 to more clearly reflect their intent.

llvm-svn: 55181

Patch contributed by Bjorn Reese!

llvm-svn: 55179

Patch contributed by m-s.

llvm-svn: 55167

so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.

llvm-svn: 55163

and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156

llvm-svn: 55154

infinite loop.

llvm-svn: 55149

Fix write() when the string being written is larger than the buffer.  This broke various ObjC testcases
with very long symbol names.

llvm-svn: 55148

llvm-svn: 55147

llvm-svn: 55146

llvm-svn: 55140

1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.

llvm-svn: 55139

llvm-svn: 55138

Fix ComputeMaskedBits to handle phis correctly.  We need to take the
minimum of the known zeros.

llvm-svn: 55137

llvm-svn: 55135

llvm-svn: 55134

llvm-svn: 55133

llvm-svn: 55130

llvm-svn: 55129

This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)

llvm-svn: 55128

operands.

llvm-svn: 55127

intptr_t type in this case. FastISel can now select simple
getelementptr instructions.

llvm-svn: 55125

from all targets.

llvm-svn: 55124

are actually deleted, so it's not necessary to remove re-used
nodes from the set.

llvm-svn: 55123

llvm-svn: 55117

slowdown in bzip2.

llvm-svn: 55113

llvm-svn: 55112

people want fast *and* correct.  Sheesh.

llvm-svn: 55102

 - Postgres
 - llvm-test/SingleSource/UnitTests/{2006-01-23-InitializedBitField,
   2004-11-28-GlobalBoolLayout, 2003-05-02-DependentPHI}

llvm-svn: 55100

llvm-svn: 55099

llvm-svn: 55097

llvm-svn: 55092

this speeds up the bcreader from 6.67s to 0.12s on a testcase Daniel 
provided.  rdar://6158117

llvm-svn: 55090

llvm-svn: 55089

llvm-svn: 55087

llvm-svn: 55085

instead of requiring an std::vector.

llvm-svn: 55084

out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.

Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.

llvm-svn: 55078