Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.

llvm-svn: 162654

llvm-svn: 162653

--as-needed.
Patch by Felix Geyer. Fixes pr13262.

llvm-svn: 162652

llvm-svn: 162649

Reviewed offline by chandlerc.

llvm-svn: 162623

llvm-svn: 162622

ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.

llvm-svn: 162615

Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

llvm-svn: 162614

It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.

This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.

llvm-svn: 162603

Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

llvm-svn: 162599

The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.

The argument registers should be added as implicit uses.

llvm-svn: 162593

There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.

llvm-svn: 162592

It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.

llvm-svn: 162591

llvm-svn: 162589

second operand is MipsISD::GPRel.

llvm-svn: 162584

llvm-svn: 162578

ProfileDataTypes.h header.

With this patch the old and new profiling code can exist side-by-side. The new
profiling code will be submitted soon and it only supports insert-edge-profiling
for now and will not depend on ProfileInfo.

Patch by Alastair Murray.

llvm-svn: 162576

the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.

llvm-svn: 162572

It is now allowed to explicitly set hasSideEffects, mayStore, and
mayLoad on instructions with patterns.

Verify that the patterns are consistent with the explicit flags.

llvm-svn: 162569

[asan/tsan] rename FunctionBlackList* to BlackList* as this class is not limited to functions any more

llvm-svn: 162566

[asan/tsan] extend the functionality of FunctionBlackList to globals and modules. Patch by Reid Watson. 

llvm-svn: 162565

In collaboration with Adhemerval Zanella.

llvm-svn: 162562

No intended behavior change.  This was introduced in r162023.  With the fixed
algorithm a Release build of ARMInstPrinter.cpp goes from 16s to 10s on a
2011 MBP.

llvm-svn: 162559

llvm-svn: 162558

llvm-svn: 162557

llvm-svn: 162556

MSVC doesn't support passing by-value parameters with alignment of
16-bytes or higher apparantly. What is deeply confusing is that it seems
to *sometimes* (but not always) apply this to any type whose alignment
is set using __declspec(align(...)). This caused lots of errors when we switch
SmallVector over to use the automatically aligned character array
utilities as they used __declspec(align(...)) heavily.

As a pretty horrible but effective work-around, we instead cherry pick
the smallest alignment sizes with specific types that happen to have the
correct alignment, and then fall back to the attribute solution past
them. This should resolve the MSVC build errors folks have been hitting.
Sorry for that. In good news, it will do this without introducing other
UB I hope. =]

Thanks to Timur Iskhodzhanov for helping me test this!

llvm-svn: 162549

llvm-svn: 162534

not in darwin gdb compat mode.

Fixes rdar://10975088

llvm-svn: 162526

TODO: Fix code duplication and coding style.
llvm-svn: 162525

llvm-svn: 162524

llvm-svn: 162520

llvm-svn: 162518

They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

llvm-svn: 162517

Emit TableGen errors if guessInstructionProperties is 0 and
instruction properties can't be inferred from patterns.

Allow explicit instruction properties even when they can be inferred.

This patch doesn't change the TableGen output. Redundant properties
are not yet verified because the tree has errors.

llvm-svn: 162516

llvm-svn: 162515

llvm-svn: 162514

Fix undefined behavior (signed integer overflow) when Clang parses a hexfloat with an enormous exponent. Caught by an existing unit test + -ftrapv.

llvm-svn: 162505

llvm-svn: 162499

llvm-svn: 162498