llvm-svn: 80707

llvm-svn: 80656

The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117

llvm-svn: 79742

llvm-svn: 79625

llvm-svn: 79622

vector shuffles.  Temporarily remove the tests for these operations until the
new implementation is working.

llvm-svn: 79579

llvm-svn: 79022

target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993

llvm-svn: 78948

llvm-svn: 78790

Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761

llvm-svn: 78745

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78666

match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658

the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646

node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615

llvm-svn: 78610

llvm-svn: 78594

llvm-svn: 78468

so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460

directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459

It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361

llvm-svn: 78330

These operations will have to be synthesized from other instructions.

llvm-svn: 78263

Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136

Add a testcase.

llvm-svn: 77992

llvm-svn: 77764

llvm-svn: 77632

llvm-svn: 77622

Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.

llvm-svn: 77172

Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types.  More to come.

llvm-svn: 77011

Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.

llvm-svn: 76919

llvm-svn: 76803

llvm-svn: 76762

llvm-svn: 76520

llvm-svn: 76424

llvm-svn: 75789

llvm-svn: 75703