This fixes PR5031. Unfortunately, there is no small testcase :(

llvm-svn: 82643

Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.

llvm-svn: 82311

Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273

llvm-svn: 82074

llvm-svn: 81969

llvm-svn: 81966

Radar 7200803.  (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)

llvm-svn: 81959

See the bug report for details.

llvm-svn: 81397

llvm-svn: 81262

Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.

llvm-svn: 80904

llvm-svn: 80773

llvm-svn: 80707

llvm-svn: 80656

makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.

Objective C++ code could generate function names that broke the previous
scheme. This fixes that.

llvm-svn: 80649

Remove the assertion and generalize the code for ARM NEON stuff.

llvm-svn: 80498

llvm-svn: 80409

Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.

llvm-svn: 80404

scalar_to_vector is fully legal now

llvm-svn: 80251

No idea whether this is profitable or not.

llvm-svn: 80245

The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117

llvm-svn: 80107

construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.

llvm-svn: 79719

now using shuffles instead of intrinsics.

llvm-svn: 79673

llvm-svn: 79625

llvm-svn: 79624

llvm-svn: 79622

llvm-svn: 79621

llvm-svn: 79620

Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle

llvm-svn: 79619

This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428

llvm-svn: 79136

llvm-svn: 79135

support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127

llvm-svn: 79084

libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

llvm-svn: 79033

llvm-svn: 79032

llvm-svn: 79026

implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.

llvm-svn: 78995

scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994

target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993