llvm-svn: 82657

constraint the register usage.

llvm-svn: 81635

llvm-svn: 81262

makes the code faster.

llvm-svn: 81220

llvm-svn: 80838

llvm-svn: 80707

llvm-svn: 80656

llvm-svn: 80502

llvm-svn: 80408

llvm-svn: 80250

No idea whether this is profitable or not.

llvm-svn: 80245

llvm-svn: 80015

llvm-svn: 80011

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

llvm-svn: 79625

llvm-svn: 79622

llvm-svn: 79620

This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428

scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994

target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993

to fix it tonight.

llvm-svn: 78896

llvm-svn: 78852

llvm-svn: 78850

llvm-svn: 78835

leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.

llvm-svn: 78815

Set "mayLoad" and "mayStore" on the load/store instructions.

llvm-svn: 78761

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646

llvm-svn: 78632

llvm-svn: 78629

llvm-svn: 78610

llvm-svn: 78604

'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514

Did anyone tests v4f32 ever?

llvm-svn: 78470

llvm-svn: 78469

llvm-svn: 78468

so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460

directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459

llvm-svn: 78425

llvm-svn: 78419