llvm-svn: 52308

and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044

load-folding table entries for PMULDQ and PMULLD.

llvm-svn: 51489

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091

"is{Trivially,Really}ReMaterializable" methods.

llvm-svn: 51001

llvm-svn: 50578

Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.

llvm-svn: 50574

llvm-svn: 50007

llvm-svn: 49830

Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented

llvm-svn: 49809

review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348

ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.

llvm-svn: 49059

llvm-svn: 49054

llvm-svn: 49037

llvm-svn: 49002

llvm-svn: 48995

llvm-svn: 48977

llvm-svn: 48922

llvm-svn: 48911

llvm-svn: 48856

llvm-svn: 48855

llvm-svn: 48854

other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777

ST(0)/ST(1).

llvm-svn: 48634

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

llvm-svn: 48412

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

llvm-svn: 48241

llvm-svn: 48240

llvm-svn: 48224

llvm-svn: 48199

llvm-svn: 48167

Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130

an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107

RST -> RFP{32/64/80}.  We only handle ST(0) for now.

llvm-svn: 48104

llvm-svn: 48101

llvm-svn: 47524

No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.

llvm-svn: 47522

llvm-svn: 47476

llvm-svn: 47043

It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.

llvm-svn: 46893