This patch splits X86_64Target specific code so that 
the dynamic atoms and the Relocation handlers are in seperate 
files for easier maintenace. The files are sure to grow and this 
makes it easier to work with.

* There is no change in functionality *

llvm-svn: 182076

llvm-svn: 182075

llvm-svn: 182074

instantiate the inherited constructor template and mark that as the constructor
which the instantiated specialization is inheriting. This fixes a
crash-on-valid when trying to compute the exception specification of a
specialization of the inheriting constructor.

llvm-svn: 182072

The analyzer can't see the reference count for shared_ptr, so it doesn't
know whether a given destruction is going to delete the referenced object.
This leads to spurious leak and use-after-free warnings.

For now, just ban destructors named '~shared_ptr', which catches
std::shared_ptr, std::tr1::shared_ptr, and boost::shared_ptr.

PR15987

llvm-svn: 182071

AST dumping: if a declaration has an uncomputed or uninstantiated exception specification, include that in the dump.

llvm-svn: 182070

Comment out ObjectFileELF::GetModuleSpecifications() function until I can debug where it's causing tests to fail.

llvm-svn: 182069

rdar://problem/13916722

llvm-svn: 182068

"source list -n <func>" can now show more than one location that matches a function name. It will unique multiple of the same source locations so they don't get displayed. It also handles inline functions correctly.

llvm-svn: 182067

Show variables that were in the debug info but optimized out. Also display a good error message when one of these variables get used in an expression.

llvm-svn: 182066

Implement ObjectFileELF::GetModuleSpecifications(), and add PlatformLinux code to deal with unknown arch properties.

CR: Greg Clayton
llvm-svn: 182065

llvm-svn: 182064

llvm-svn: 182063

radar://problem/13865940

llvm-svn: 182062

llvm-svn: 182061

llvm-svn: 182060

Note in the documentation about the fact that Python callbacks can return a value and if that value is False, LLDB won’t stop at the breakpoint

llvm-svn: 182059

Previously, we’ve used the last location of the analyzer issue path as the location of the
report. This might not provide the best user experience, when one analyzer a source
file and the issue appears in the header. Introduce an option to use the last location
of the path that is in the main source file as the report location.

New option can be enabled with -analyzer-config report-in-main-source-file=true.

llvm-svn: 182058

#steps not #1s, and use a more traditional step count where the 'halt' step is
not counted.

llvm-svn: 182057

function call exception catching breakpoints.  We need to force ourselves to stop in
that case.

<rdar://problem/13903801>

llvm-svn: 182056

This is a modified version of a patch by Manuel Klimek.

llvm-svn: 182055

llvm-svn: 182054

Previously, three instructions were needed:

trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)

Now we need only two:

trunc.w.s $f0, $f2
swc1 $f0, 0($2)

llvm-svn: 182053

Now that we have good testing, remove addFrameMove and create cfi
instructions directly.

llvm-svn: 182052

llvm-svn: 182051

llvm-svn: 182050

We need ppc instead of generic to override native features on ppc machines.

llvm-svn: 182049

This patch removes alias definition for addiu $rs,$imm 
and instead uses the TwoOperandAliasConstraint field in 
the ArithLogicI instruction class. 

This way all instructions that inherit ArithLogicI class 
have the same macro defined. 

The usage examples are added to test files.

Patch by Vladimir Medic

llvm-svn: 182048

llvm-svn: 182047

llvm-svn: 182046

Some IR-level instructions (such as FP <-> i64 conversions) are not chained
w.r.t. the mtctr intrinsic and yet may become function calls that clobber the
counter register. At the selection-DAG level, these might be reordered with the
mtctr intrinsic causing miscompiles. To avoid this situation, if an existing
preheader has instructions that might use the counter register, create a new
preheader for the mtctr intrinsic. This extra block will be remerged with the
old preheader at the MI level, but will prevent unwanted reordering at the
selection-DAG level.

llvm-svn: 182045

llvm-svn: 182044

llvm-svn: 182043

invalid instruction sequence.

Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.

mtc1 $f4, $4         # int-to-fp move instruction.
mov.s $f2, $f4       # move contents of $f4 to $f2.
cvt.s.w $f0, $f2     # int-to-fp conversion.

llvm-svn: 182042

llvm-svn: 182041

This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm

The corresponding test cases are added.

Patch by Vladimir Medic

llvm-svn: 182040

synthesize a property getter method that overrides
a method definition named 'retain' and the like.
Fixes // rdar://13885083

llvm-svn: 182039

if ((x & 255) == 255)

before: movzbl  %al, %eax
        cmpl  $255, %eax

after:  cmpb  $-1, %al
llvm-svn: 182038

llvm-svn: 182036

llvm-svn: 182035