- Sep 06, 2008
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Eli Friedman authored
i32>. This is a little messy, but it works. We should really get rid of the intrinsics, though, since they map perfectly well to standard LLVM instructions. llvm-svn: 55864
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- Aug 28, 2008
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Evan Cheng authored
llvm-svn: 55466
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- Aug 20, 2008
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Dan Gohman authored
necessary to use dyn_cast in these predicates. llvm-svn: 55055
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- Aug 08, 2008
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Dan Gohman authored
X86ISelLowering creates. llvm-svn: 54544
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- Aug 06, 2008
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Evan Cheng authored
llvm-svn: 54376
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- Jul 17, 2008
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Nate Begeman authored
llvm-svn: 53720
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Nate Begeman authored
llvm-svn: 53719
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- Jul 10, 2008
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Evan Cheng authored
llvm-svn: 53386
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- Jun 16, 2008
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Evan Cheng authored
llvm-svn: 52363
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Evan Cheng authored
llvm-svn: 52352
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- Jun 13, 2008
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Duncan Sands authored
wrong for volatile loads and stores. In fact this is almost all of them! There are three types of problems: (1) it is wrong to change the width of a volatile memory access. These may be used to do memory mapped i/o, in which case a load can have an effect even if the result is not used. Consider loading an i32 but only using the lower 8 bits. It is wrong to change this into a load of an i8, because you are no longer tickling the other three bytes. It is also unwise to make a load/store wider. For example, changing an i16 load into an i32 load is wrong no matter how aligned things are, since the fact of loading an additional 2 bytes can have i/o side-effects. (2) it is wrong to change the number of volatile load/stores: they may be counted by the hardware. (3) it is wrong to change a volatile load/store that requires one memory access into one that requires several. For example on x86-32, you can store a double in one processor operation, but to store an i64 requires two (two i32 stores). In a multi-threaded program you may want to bitcast an i64 to a double and store as a double because that will occur atomically, and be indivisible to other threads. So it would be wrong to convert the store-of-double into a store of an i64, because this will become two i32 stores - no longer atomic. My policy here is to say that the number of processor operations for an illegal operation is undefined. So it is alright to change a store of an i64 (requires at least two stores; but could be validly lowered to memcpy for example) into a store of double (one processor op). In short, if the new store is legal and has the same size then I say that the transform is ok. It would also be possible to say that transforms are always ok if before they were illegal, whether after they are illegal or not, but that's more awkward to do and I doubt it buys us anything much. However this exposed an interesting thing - on x86-32 a store of i64 is considered legal! That is because operations are marked legal by default, regardless of whether the type is legal or not. In some ways this is clever: before type legalization this means that operations on illegal types are considered legal; after type legalization there are no illegal types so now operations are only legal if they really are. But I consider this to be too cunning for mere mortals. Better to do things explicitly by testing AfterLegalize. So I have changed things so that operations with illegal types are considered illegal - indeed they can never map to a machine operation. However this means that the DAG combiner is more conservative because before it was "accidentally" performing transforms where the type was illegal because the operation was nonetheless marked legal. So in a few such places I added a check on AfterLegalize, which I suppose was actually just forgotten before. This causes the DAG combiner to do slightly more than it used to, which resulted in the X86 backend blowing up because it got a slightly surprising node it wasn't expecting, so I tweaked it. llvm-svn: 52254
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- May 29, 2008
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Evan Cheng authored
llvm-svn: 51667
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- May 28, 2008
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Dan Gohman authored
llvm-svn: 51630
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Mon P Wang authored
is a memory location llvm-svn: 51626
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- May 24, 2008
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Evan Cheng authored
llvm-svn: 51533
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Evan Cheng authored
Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles. llvm-svn: 51531
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Evan Cheng authored
Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into load and shuffle instructions. llvm-svn: 51522
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- May 23, 2008
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Evan Cheng authored
llvm-svn: 51501
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Evan Cheng authored
llvm-svn: 51490
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Dan Gohman authored
load-folding table entries for PMULDQ and PMULLD. llvm-svn: 51489
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Evan Cheng authored
Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks. Also fixed some 80 col. violations. llvm-svn: 51462
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- May 22, 2008
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Evan Cheng authored
llvm-svn: 51435
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- May 20, 2008
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Evan Cheng authored
llvm-svn: 51327
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- May 13, 2008
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Nate Begeman authored
llvm-svn: 51057
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Nate Begeman authored
llvm-svn: 51020
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Nate Begeman authored
Teach X86 a few more vsetcc patterns. Custom lowering for unsupported ones is next. llvm-svn: 51009
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- May 12, 2008
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Nate Begeman authored
llvm-svn: 51000
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- May 10, 2008
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Evan Cheng authored
llvm-svn: 50929
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Evan Cheng authored
llvm-svn: 50922
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- May 09, 2008
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Evan Cheng authored
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch. llvm-svn: 50918
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Evan Cheng authored
llvm-svn: 50874
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- May 08, 2008
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Evan Cheng authored
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. llvm-svn: 50838
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- May 03, 2008
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Evan Cheng authored
Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. llvm-svn: 50601
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- May 02, 2008
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Evan Cheng authored
llvm-svn: 50575
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- Apr 20, 2008
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Chris Lattner authored
llvm-svn: 49986
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- Apr 16, 2008
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Dan Gohman authored
puts its result in a 32-bit GPR. llvm-svn: 49762
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- Apr 10, 2008
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Chris Lattner authored
MOVZQI2PQIrr. This would be better handled as a dag combine (with the goal of eliminating the bitconvert) but I don't know how to do that safely. Thoughts welcome. llvm-svn: 49463
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- Apr 05, 2008
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Evan Cheng authored
llvm-svn: 49244
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- Mar 26, 2008
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Evan Cheng authored
llvm-svn: 48815
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- Mar 24, 2008
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Evan Cheng authored
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction. llvm-svn: 48746
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