llvm-svn: 110940

llvm-svn: 110937

Before spilling a live range, we split it into a separate range for each basic
block where it is used. That way we only get one reload per basic block if the
new smaller ranges can allocate to a register.

This type of splitting is already present in the standard spiller.

llvm-svn: 110934

having it finish processing all of the muliply operands before
starting the whole getAddExpr process over again, instead of
immediately after the first simplification.

llvm-svn: 110916

llvm-svn: 110915

by having it finish processing the whole operand list before
starting the whole getAddExpr process over again, instead of
immediately after the first duplicate is found.

llvm-svn: 110914

target triple and straightens it out.  This does less than gcc's script
config.sub, for example it turns i386-mingw32 into i386--mingw32 not
i386-pc-mingw32, but it does a decent job of turning funky triples into
something that the rest of the Triple class can understand.  The plan
is to use this to canonicalize triple's when they are first provided
by users, and have the rest of LLVM only deal with canonical triples.
Once this is done the special case workarounds in the Triple constructor
can be removed, making the class more regular and easier to use.  The
comments and unittests for the Triple class are already adjusted in this
patch appropriately for this brave new world of increased uniformity.

llvm-svn: 110909

in an external testsuite.

llvm-svn: 110905

llvm-svn: 110898

term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897

entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894

because it could have an ambiguous suffix.

llvm-svn: 110890

instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889

target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888

Added two test cases to arm-tests.txt.

llvm-svn: 110880

Tested by scope.exp in gdb testsuite.

llvm-svn: 110876

instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875

When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

llvm-svn: 110874

llvm-svn: 110863

 - remove ashr which never worked.
 - fix lshr and shl and add tests.
 - remove dead function "intersect1Wrapped".
 - add a new sub method to subtract ranges, with test.

llvm-svn: 110861

and remove casts from all its callers.

llvm-svn: 110848

llvm-svn: 110847

llvm-svn: 110843

llvm-svn: 110842

that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.

llvm-svn: 110836

avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.

llvm-svn: 110835

llvm-svn: 110826

llvm-svn: 110810

float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00

llvm-svn: 110799

Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.

llvm-svn: 110798

llvm-svn: 110797

llvm-svn: 110796

llvm-svn: 110795

MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.

llvm-svn: 110794

llvm-svn: 110793

llvm-svn: 110792

llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching.

llvm-svn: 110791

llvm-svn: 110790

llvm-svn: 110788

llvm-svn: 110787