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  1. Sep 25, 2013
    • Quentin Colombet's avatar
      [PR16882] Ignore noreturn definitions when setting isPhysRegUsed. · fa403ab3
      Quentin Colombet authored
      PEI inserts a save/restore sequence for the link register, according to the
      information it gets from the MachineRegisterInfo.
      MachineRegisterInfo is populated by the VirtRegMap pass.
      This pass was not aware of noreturn calls and was registering the definitions of
      these calls the same way as regular operations.
      
      Modify VirtRegPass so that it does not set the isPhysRegUsed information for
      registers only defined by noreturn calls.
      The rational is that a noreturn call is the "last instruction" of the program
      (if it returns the behavior is undefined), so everything that is defined by it
      cannot be used and will not interfere with anything else. Therefore, it is
      pointless to account for then.
      
      llvm-svn: 191349
      fa403ab3
    • Eli Friedman's avatar
      Add missing check to SETCC optimization. · a961d694
      Eli Friedman authored
      PR17338.
      
      llvm-svn: 191337
      a961d694
  2. Sep 24, 2013
  3. Sep 23, 2013
    • Bill Wendling's avatar
      Reformat code with clang-format. · 8faa30ef
      Bill Wendling authored
      llvm-svn: 191226
      8faa30ef
    • Eric Christopher's avatar
      Handle gnu pubtypes sections: · 261d2343
      Eric Christopher authored
      a) Make sure we are emitting the correct section in our section labels
      when we begin the module.
      b) Make sure we are emitting the correct pubtypes section in the
      presence of gnu pubtypes.
      c) For C++ struct, union, class, and enumeration types are default
      external.
      
      llvm-svn: 191225
      261d2343
    • Kay Tiong Khoo's avatar
      fix typo: than -> then · 9195a5b0
      Kay Tiong Khoo authored
      llvm-svn: 191214
      9195a5b0
    • Richard Mitton's avatar
      Fixed debug_aranges handling for common symbols. · 089ed89e
      Richard Mitton authored
      The size of common symbols is now tracked correctly, so they can be listed in the arange section without needing knowledge of other following symbols.
      
      .comm (and .lcomm) do not indicate to the system assembler any particular section to use, so we have to treat them as having no section.
      
      Test case update to account for this.
      
      llvm-svn: 191210
      089ed89e
  4. Sep 22, 2013
    • Benjamin Kramer's avatar
      Provide basic type safety for array_pod_sort comparators. · 8817cca5
      Benjamin Kramer authored
      This makes using array_pod_sort significantly safer. The implementation relies
      on function pointer casting but that should be safe as we're dealing with void*
      here.
      
      llvm-svn: 191175
      8817cca5
    • Tim Northover's avatar
      ISelDAG: spot chain cycles involving MachineNodes · 31d093c7
      Tim Northover authored
      Previously, the DAGISel function WalkChainUsers was spotting that it
      had entered already-selected territory by whether a node was a
      MachineNode (amongst other things). Since it's fairly common practice
      to insert MachineNodes during ISelLowering, this was not the correct
      check.
      
      Looking around, it seems that other nodes get their NodeId set to -1
      upon selection, so this makes sure the same thing happens to all
      MachineNodes and uses that characteristic to determine whether we
      should stop looking for a loop during selection.
      
      This should fix PR15840.
      
      llvm-svn: 191165
      31d093c7
  5. Sep 21, 2013
  6. Sep 20, 2013
  7. Sep 19, 2013
  8. Sep 17, 2013
    • Arnold Schwaighofer's avatar
      Costmodel: Add support for horizontal vector reductions · cae8735a
      Arnold Schwaighofer authored
      Upcoming SLP vectorization improvements will want to be able to estimate costs
      of horizontal reductions. Add infrastructure to support this.
      
      We model reductions as a series of (shufflevector,add) tuples ultimately
      followed by an extractelement. For example, for an add-reduction of <4 x float>
      we could generate the following sequence:
      
       (v0, v1, v2, v3)
         \   \  /  /
           \  \  /
             +  +
      
       (v0+v2, v1+v3, undef, undef)
          \      /
       ((v0+v2) + (v1+v3), undef, undef)
      
       %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
                                 <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
       %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
       %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
                                <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
       %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
       %r = extractelement <4 x float> %bin.rdx8, i32 0
      
      This commit adds a cost model interface "getReductionCost(Opcode, Ty, Pairwise)"
      that will allow clients to ask for the cost of such a reduction (as backends
      might generate more efficient code than the cost of the individual instructions
      summed up). This interface is excercised by the CostModel analysis pass which
      looks for reduction patterns like the one above - starting at extractelements -
      and if it sees a matching sequence will call the cost model interface.
      
      We will also support a second form of pairwise reduction that is well supported
      on common architectures (haddps, vpadd, faddp).
      
       (v0, v1, v2, v3)
        \   /    \  /
       (v0+v1, v2+v3, undef, undef)
          \     /
       ((v0+v1)+(v2+v3), undef, undef, undef)
      
        %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
              <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
        %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
              <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
        %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
        %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
              <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
        %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
              <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
        %bin.rdx.1 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
        %r = extractelement <4 x float> %bin.rdx.1, i32 0
      
      llvm-svn: 190876
      cae8735a
    • Serge Pavlov's avatar
      Added documentation to getMemsetStores. · 8ec39992
      Serge Pavlov authored
      llvm-svn: 190866
      8ec39992
    • Quentin Colombet's avatar
      [SelectionDAG] Teach the vector scalarizer about TRUNCATE. · d30a9585
      Quentin Colombet authored
      When a truncate node defines a legal vector type but uses an illegal
      vector type, the legalization process was splitting the vector until
      <1 x vector> type, but then it was failing to scalarize the node because
      it did not know how to handle TRUNCATE.
      
      <rdar://problem/14989896>
      
      llvm-svn: 190830
      d30a9585
    • Adrian Prantl's avatar
      Debug info: Fix PR16736 and rdar://problem/14990587. · db3e26d1
      Adrian Prantl authored
      A DBG_VALUE is register-indirect iff the first operand is a register
      _and_ the second operand is an immediate.
      
      llvm-svn: 190821
      db3e26d1
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