llvm-svn: 137321

llvm-svn: 137320

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318

llvm-svn: 137317

Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316

llvm-svn: 137313

lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310

(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308

It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303

llvm-svn: 137297

infinite recursive calls in legalize. Fix PR10562

llvm-svn: 137296

could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295

Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases.  This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).

Fixes PR9693.

llvm-svn: 137292

llvm-svn: 137283

llvm-svn: 137282

llvm-svn: 137277

An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.

- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
  nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
  once. This is because unloop no longer has a backedge and blocks
  within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
  their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
  each immediate subloop has a new parent.

llvm-svn: 137276

llvm-svn: 137260

Add support for literal encoding of #-0 along the way.

llvm-svn: 137254

Distinguish between two copies of one inlined variable. Take 2.

llvm-svn: 137253

While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.

llvm-svn: 137250

llvm-svn: 137249

llvm-svn: 137246

llvm-svn: 137245

llvm-svn: 137244

data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238

llvm-svn: 137237

llvm-svn: 137236

Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.

llvm-svn: 137229

def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

llvm-svn: 137227

llvm-svn: 137226

llvm-svn: 137225

llvm-svn: 137224

Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses.  Hopefully this fixes some buildbots.

llvm-svn: 137223

llvm-svn: 137217

llvm-svn: 137204

llvm-svn: 137203

SimplifyIndVar utility since it is required.

llvm-svn: 137202

llvm-svn: 137199

llvm-svn: 137198