llvm-svn: 155211

Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.

llvm-svn: 155210

Add debugging hints for when bugpoint does not suffice, specifically for instcombine and TargetLowering

llvm-svn: 155209

 - Also, drop the lines.gif background from doxygen, this URL was wrong on the
   llvm.org server anyway.

llvm-svn: 155208

llvm-svn: 155206

llvm-svn: 155203

llvm-svn: 155202

llvm-svn: 155199

llvm-svn: 155197

llvm-svn: 155195

(load only has one operand) and smuggle in some whitespace changes too

NB: I am obviously testing the water here, and believe that the unguarded
    cast is still wrong, but why is the getZExtValue of the load's operand
    tested against zero here? Any review is appreciated.
llvm-svn: 155190

Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

llvm-svn: 155188

Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

llvm-svn: 155186

While the patch was perfect and defect free, it exposed a really nasty
bug in X86 SelectionDAG that caused an llc crash when compiling lencod.

I'll put the patch back in after fixing the SelectionDAG problem.

llvm-svn: 155181

llvm-svn: 155178

llvm-svn: 155177

No need for these explicit aliases anymore. Nuke 'em.

llvm-svn: 155173

Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
  add {Rd}, Rn, Rm  // Rd is optional and is the same as Rn if omitted.

The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.

rdar://11255754

llvm-svn: 155172

llvm-svn: 155166

Now that llvm-config is a binary instead of a script the version installed
during a cross compiled build cannot be run from the host.  When cross
compiling, install a separate llvm-config-host that will run on the host.

llvm-svn: 155164

loop repeatedlt making the same change. This is for rdar://11256239.

llvm-svn: 155160

when the set bits aren't the same for both args of the xor.
This transformation is in the function TargetLowering::SimplifyDemandedBits
in the file lib/CodeGen/SelectionDAG/TargetLowering.cpp.

I have tested this test using a previous version of llc which the defect and 
the a version of llc which does not. I got the expected fail and pass, 
respectively.

This test goes with rdar://11195364 and the check in with the fix: svn r154955

llvm-svn: 155156

llvm-svn: 155153

llvm-svn: 155151

llvm-ld is no longer useful and causes confusion and so it is being removed.

* Does not work very well on Windows because it must call a gcc like driver to
  assemble and link.
* Has lots of hard coded paths which are wrong on many systems.
* Does not understand most of ld's options.
* Can be partially replaced by llvm-link | opt | {llc | as, llc -filetype=obj} |
  ld, or fully replaced by Clang.

I know of no production use of llvm-ld, and hacking use should be
replaced by Clang's driver.

llvm-svn: 155147

There's almost always a small number of instruction operands, so
use a SmallVector and save on heap allocations.

llvm-svn: 155143

llvm-svn: 155142

The shl instruction is used to represent multiplication by a constant
power of two as well as bitwise left shifts. Some InstCombine
transformations would turn an shl instruction into a bit mask operation,
making it difficult for later analysis passes to recognize the
constsnt multiplication.

Disable those shl transformations, deferring them to DAGCombine time.
An 'shl X, C' instruction is now treated mostly the same was as 'mul X, C'.

These transformations are deferred:

  (X >>? C) << C   --> X & (-1 << C)  (When X >> C has multiple uses)
  (X >>? C1) << C2 --> X << (C2-C1) & (-1 << C2)   (When C2 > C1)
  (X >>? C1) << C2 --> X >>? (C1-C2) & (-1 << C2)  (When C1 > C2)

The corresponding exact transformations are preserved, just like
div-exact + mul:

  (X >>?,exact C) << C   --> X
  (X >>?,exact C1) << C2 --> X << (C2-C1)
  (X >>?,exact C1) << C2 --> X >>?,exact (C1-C2)

The disabled transformations could also prevent the instruction selector
from recognizing rotate patterns in hash functions and cryptographic
primitives. I have a test case for that, but it is too fragile.

llvm-svn: 155136

llvm-svn: 155134

 - Work in progress, this is mostly important because it lets us incrementally migrate the remaining documentation.
 - Lots of styling, editing, and integration work yet to come…
 - PR12589

llvm-svn: 155133

 - Work in progress, this is just the basic structure.

llvm-svn: 155132

the user has another lit somewhere.

llvm-svn: 155131

llvm-svn: 155128

Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away.

llvm-svn: 155104

llvm-svn: 155090

llvm-svn: 155089

llvm-svn: 155081

llvm-svn: 155075

symbolicated.  These have and operand type of TYPE_RELv which was not handled
as isBranch in translateImmediate() in X86Disassembler.cpp.  rdar://11268426 

llvm-svn: 155074

a function with arguments. This fixes rdar://11265785.

llvm-svn: 155073