llvm-svn: 15377

llvm-svn: 15371

llvm-svn: 15365

llvm-svn: 15364

llvm-svn: 15363

llvm-svn: 15362

or return intructions.

llvm-svn: 15356

llvm-svn: 15240

llvm-svn: 15239

All CVS history was renamed, the *,v were copied over.  No worries.

llvm-svn: 15238

again in the future, it can be resurrected out of CVS

llvm-svn: 15112

        mov %EDI, 12
        add %EDI, %ECX
        mov %ECX, 12
        add %ECX, %EDX
        mov %EDX, 12
        add %EDX, %ESI

instead (really!) generate this:

        add %ECX, 12
        add %EDX, 12
        add %ESI, 12

llvm-svn: 15090

llvm-svn: 15013

llvm-svn: 15012

- Replace ConstantPointerRef usage with GlobalValue usage
- Minimize redundant isa<GlobalValue> usage
- Correct isa<Constant> for GlobalValue subclass

llvm-svn: 14950

shrd [mem], reg, imm

This fixes the jit-ls failure on 186.crafty.

llvm-svn: 14914

llvm-svn: 14913

llvm-svn: 14841

this LLVM function:

int %foo() {
        ret int cast (int** getelementptr (int** null, int 1) to int)
}

into:

foo:
        mov %EAX, 0
        lea %EAX, DWORD PTR [%EAX + 4]
        ret

now we compile it into:

foo:
        mov %EAX, 4
        ret

This sequence is frequently generated by the MSIL front-end, and soon the malloc lowering pass and
Java front-ends as well..

-Chris

llvm-svn: 14834

The shared command line options are now in a header that makes sense.

llvm-svn: 14756

llvm-svn: 14747

llvm-svn: 14745

llvm-svn: 14622

llvm-svn: 14564

llvm-svn: 14483

llvm-svn: 14482

this is a bug, and should be fixed.

llvm-svn: 14476

float as a truncation by going through memory.  This truncation was being
skipped, which caused 175.vpr to fail after aggressive register promotion.

llvm-svn: 14473

Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.

llvm-svn: 14389

llvm-svn: 14299

llvm-svn: 14298

llvm-svn: 14266

mov REG, C
sub REG, X

generate:

neg X
add X, C

which uses one less reg

llvm-svn: 14213

the setcc.

llvm-svn: 14212

we do not want to fold the load in cases like this:

  X = load
    = add A, X
    = add B, X

llvm-svn: 14204

llvm-svn: 14201

llvm-svn: 14189

llvm-svn: 14185

comparisons.  In an 'isunordered' predicate, which looks like this at
the LLVM level:

        %a = call bool %llvm.isnan(double %X)
        %b = call bool %llvm.isnan(double %Y)
        %COM = or bool %a, %b

We used to generate this code:

        fxch %ST(1)
        fucomip %ST(0), %ST(0)
        setp %AL
        fucomip %ST(0), %ST(0)
        setp %AH
        or %AL, %AH

With this patch, we generate this code:

        fucomip %ST(0), %ST(1)
        fstp %ST(0)
        setp %AL

Which should make alkis happy.  Tested as X86/compare_folding.llx:test1

llvm-svn: 14148

llvm-svn: 14146