Introduce the VEX_X field

llvm-svn: 105859

that rip-relative address when executing in 32-bit mode.

llvm-svn: 105656

immediates to avoid breaking the build.

llvm-svn: 105652

In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524

yet, only assembly encoding support.

llvm-svn: 105521

llvm-svn: 98954

were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880

llvm-svn: 98855

files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839

not the end of the field, fixing rdar://7651978

llvm-svn: 96330

encoding them into nothing.

llvm-svn: 96110

llvm-svn: 96088

llvm-svn: 96076

fix swapgs to be spelled right.

llvm-svn: 96058

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

rip-relative addresses, and add a testcase.

llvm-svn: 96040

llvm-svn: 96038

addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

llvm-svn: 96031

llvm-svn: 96029

llvm-svn: 96028

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.

llvm-svn: 95929

the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.

llvm-svn: 95924

llvm-svn: 95920

use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901

fixes the remaining x86-64 jit failures afaik.

llvm-svn: 95867

r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.

This fixes x86-64 jit miscompilations of a bunch of programs.

llvm-svn: 95866

Stub out some dummy fixups to make things work.

We can now emit fixups like this:
	subl	$20, %esp               ## encoding: [0x83,0xec,A]
                                        ##   fixup A - offset: 2, value: 20, kind: fixup_1byte_imm

Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which 
should be producing an imm of 20, not an MCExpr of 20.

llvm-svn: 95860

and rename it to EmitImmediate.

llvm-svn: 95859

llvm-svn: 95858

llvm-svn: 95857

displacement values.

llvm-svn: 95773

throughout the X86 encoder.

llvm-svn: 95771

even for the immediate case.  No functionality change.

llvm-svn: 95770

llvm-svn: 95708

llvm-svn: 95699

llvm-svn: 95445

llvm-svn: 95440