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  1. Jun 16, 2011
    • Jakub Staszak's avatar
      Test commit. · feadd435
      Jakub Staszak authored
      llvm-svn: 133174
      feadd435
    • Jakob Stoklund Olesen's avatar
      Add TargetRegisterInfo::getRawAllocationOrder(). · 1f641d57
      Jakob Stoklund Olesen authored
      This virtual function will replace allocation_order_begin/end as the one
      to override when implementing custom allocation orders. It is simpler to
      have one function return an ArrayRef than having two virtual functions
      computing different ends of the same array.
      
      Use getRawAllocationOrder() in place of allocation_order_begin() where
      it makes sense, but leave some clients that look like they really want
      the filtered allocation orders from RegisterClassInfo.
      
      llvm-svn: 133170
      1f641d57
    • Nick Lewycky's avatar
      Add a DAGCombine for (ext (binop (load x), cst)). · 6d677cfd
      Nick Lewycky authored
      llvm-svn: 133124
      6d677cfd
    • Anna Zaks's avatar
      Function::getNumBlockIDs() should be used instead of Function::size() to set... · 2c2aa9a9
      Anna Zaks authored
      Function::getNumBlockIDs() should be used instead of Function::size() to set the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix).
      
      llvm-svn: 133113
      2c2aa9a9
    • John McCall's avatar
      The ARC language-specific optimizer. Credit to Dan Gohman. · d935e9c3
      John McCall authored
      llvm-svn: 133108
      d935e9c3
    • Owen Anderson's avatar
      Add a new MVT::untyped. This will be used in future work for modelling ISA... · 96adc4a5
      Owen Anderson authored
      Add a new MVT::untyped.  This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers).  We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them.  Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
      
      llvm-svn: 133106
      96adc4a5
  2. Jun 15, 2011
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