llvm-svn: 41608

Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses.

llvm-svn: 41599

llvm-svn: 41510

to not alias each other, it can be translated as an llvm.memcpy.

llvm-svn: 41489

Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)

llvm-svn: 41479

llvm-svn: 41164

llvm-svn: 41135

Update test: dynamic_stackalloc size *must* be rounded to ensure stack ptr be left in a valid state.

llvm-svn: 41134

llvm-svn: 41123

llvm-svn: 41100

llvm-svn: 41099

regex used to convert all the others because the first '|' was on a
separate line.

llvm-svn: 41098

llvm-svn: 41097

llvm-svn: 41073

using the count script instead of wc -l

llvm-svn: 41072

llvm-svn: 41070

llvm-svn: 41068

llvm-svn: 41061

see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049

llvm-svn: 41048

llvm-svn: 41012

Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).

llvm-svn: 41010

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.

llvm-svn: 40987

llvm-svn: 40846

Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756

X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736

llvm-svn: 40721

llvm-svn: 40690

llvm-svn: 40675

llvm-svn: 40657

mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648

Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )

llvm-svn: 40628

Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555

llvm-svn: 40547

llvm-svn: 40539

llvm-svn: 40536

x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504

register instead of loading each element individually.

llvm-svn: 40478

for everything.

llvm-svn: 40101