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Unverified Commit 3af82b39 authored by sstwcw's avatar sstwcw Committed by GitHub
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[clang-format] Add spaces around the Verilog implication operator (#71352)

The Verilog implication operator `->` is a binary operator meaning
either the left hand side is false or the right hand side is true.
Previously it was treated as the C++ struct member operator.

I didn't even know it existed when I added the operator formatting part.
And I didn't check all the tests for all the operators I added. That is
how the bad test got in.
parent 0468867c
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