[AArch64][SME] Update load/store intrinsics to take predicate corresponding to element size.

Instead of using <vscale x 16 x i1> for all the loads/stores, we now use the appropriate
predicate type according to the element size, e.g.

  ld1b uses <vscale x 16 x i1>
  ld1w uses <vscale x 4 x i1>
  ld1q uses <vscale x 1 x i1>

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D129083