[RISCV] Add a test case where mutation still violates strict asserts in InsertVSETVLI

This is the test which triggered my disabling of the assert in d4545e6f.  The
issue it reveals is basically the same as from cc0283a6, but in the cross
block case.

We visit block1, mutate the setvli (correctly), and then visit block two and
ask whether the vadd is compatible with the block state.  Before mutation, it
wasn't.  After mutation, it is.  And thus, we have our phase 1 vs 3 difference.