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Commit 82d330e0 authored by Jingu Kang's avatar Jingu Kang
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[AArch64] Try to convert vector shift operation into vector add operation

The vector shift instructions tend to be worse than ADD/SUB on AArch64 cores
so this patch supports tablegen patterns for below simple transformation.

 x << 1 ==> x + x

Differential Revision: https://reviews.llvm.org/D153049
parent ed34cb2c
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