[AArch64][CodeGen] Lower (de)interleave2 intrinsics to ld2/st2

The InterleavedAccess pass currently matches (de)interleaving
shufflevector instructions with loads or stores, and calls into
target lowering to generate ldN or stN instructions.

Since we can't use shufflevector for scalable vectors (besides a
splat with zeroinitializer), we have interleave2 and deinterleave2
intrinsics. This patch extends InterleavedAccess to recognize those
intrinsics and if possible replace them with ld2/st2.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D146218