Commits · 0731372ee25c8db93e0d976db4be4ffb7c7329c5 · Roger Ferrer / llvm-epi · GitLab

Mar 26, 2020
- [X86] Prefer PACKUS(AND(),AND()) to SHUFFLE(PSHUFB(),PSHUFB()) on all targets · ad36491e
  Simon Pilgrim authored Mar 26, 2020
  ad36491e
- [X86] lowerV16I8Shuffle - create v8i16 mask for PACKUS(AND(),AND()) patterns. · 39a52a19
  Simon Pilgrim authored Mar 26, 2020
  39a52a19
- [AIX] discard the label in the csect of function description and use qualname for linkage · fdfe411e
  diggerlin authored Mar 26, 2020
  fdfe411e
- [InstCombine] add shuffle-with-bitcast-operand tests; NFC · 5237262f
  Sanjay Patel authored Mar 25, 2020
  
  5237262f
- [InstCombine] Fix Incorrect fold of ashr+xor -> lshr w/ vectors · 7a89a5d8
  Jon Roelofs authored Mar 25, 2020
  7a89a5d8
- [PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32 · 459e8e94
  Justin Hibbits authored Mar 23, 2020
  459e8e94
- [X86][SSE] Prefer PACKUS(AND(),AND()) to SHUFFLE(PSHUFB(),PSHUFB()) on pre-AVX2 targets · 9d1721ce
  Simon Pilgrim authored Mar 26, 2020
  9d1721ce
- [PPCInstPrinter] Change printBranchOperand(calltarget) to print the target... · 3eef4740
  Fangrui Song authored Mar 22, 2020
  3eef4740
- [X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form · 87de9a07
  Fangrui Song authored Mar 22, 2020
  87de9a07
- [Legalizer] Fix some flags miss in vector results · 172456c7
  Qiu Chaofan authored Mar 26, 2020
  172456c7
- [NFC] Create X86 subdirectory for indvar tests · db8a3c42
  Sam Parker authored Mar 26, 2020
  db8a3c42
- [X86][SSE] getFauxShuffleMask - peek through TRUNCATE/AEXT/ZEXT for... · e30d29eb
  Simon Pilgrim authored Mar 26, 2020
  e30d29eb
- [PowerPC] Remove the repeated definition for some InstAlias for mtspr/mfspr · 4673699a
  Kang Zhang authored Mar 26, 2020
  4673699a
- [AArch64][SVE] Implement structured store intrinsics · 9086db70
  Cullen Rhodes authored Mar 25, 2020
  9086db70
- [PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support · 71ae267d
  Ties Stuij authored Mar 26, 2020
  71ae267d
- [ARM] Sink splats to vector float instructions · 37b9cc8f
  David Green authored Mar 25, 2020
  37b9cc8f
- [X86] Update more intrinsic tests to prepare to extend D60940 to scalar fp. · 281015de
  Craig Topper authored Mar 25, 2020
  281015de
- Use optimal layout and preserve alloca alignment in coroutine frames. · 9514c048
  John McCall authored Mar 25, 2020
  9514c048
- [PowerPC] Improve the way legalize mul for v8i16 and add pattern to match mul + add · 1ef7bf41
  QingShan Zhang authored Mar 26, 2020
  1ef7bf41
- [X86] Split more masked instruction tests to enable D60940. · 31c5afb3
  Craig Topper authored Mar 25, 2020
  31c5afb3
- Relax newly added opcode checks to check only for a number instead of a specific opcode. · d622612e
  Douglas Yung authored Mar 25, 2020
  
  d622612e
- [AMDGPU] Fixed function traversal in attribute propagation · e06d707a
  Stanislav Mekhanoshin authored Mar 25, 2020
  e06d707a
Mar 25, 2020
- [AMDGPU] Preserve original symbol during attribute propagation · 6e00e3fc
  Stanislav Mekhanoshin authored Mar 25, 2020
  6e00e3fc
- [SCCP] Add a few constantexpr,undef tests for cond propagation · 081efa7d
  Florian Hahn authored Mar 24, 2020
  
  081efa7d
- Ignore/Drop droppable uses for code-sinking in InstCombine · f1a9efab
  Tyker authored Mar 25, 2020
  f1a9efab
- [ThinLTO] Don't rely on debug output for thinlto_samplepgo_icp3 test · 934d4fea
  Alexandre Ganea authored Mar 25, 2020
  934d4fea
- [X86][AVX] Combine shuffles to TRUNCATE/VTRUNC patterns · c6e5531f
  Simon Pilgrim authored Mar 25, 2020
  c6e5531f
- [ARM,CDE] Implement predicated Q-register CDE intrinsics · bb4da94e
  Mikhail Maltsev authored Mar 25, 2020
  bb4da94e
- [ARM] Move ConstantIsland and LowOverheadLoops Passes. · bd069ad3
  Yvan Roux authored Mar 25, 2020
  bd069ad3
- [AMDGPU] Add SIPreEmitPeephole pass. · ce984129
  cdevadas authored Mar 25, 2020
  ce984129
- [X86][AVX] Add common prefix to merge 32/64-bit AVX1 checks · 146df558
  Simon Pilgrim authored Mar 25, 2020
  
  146df558
- [SystemZ] Improve foldMemoryOperandImpl() · f09b891d
  Jonas Paulsson authored Mar 11, 2020
  f09b891d
- [PowerPC][AIX] ByVal formal arguments in a single register. · 3282d875
  Sean Fertile authored Mar 25, 2020
  3282d875
- [VectorCombine] add shuffle tests; NFC · f631b9dc
  Sanjay Patel authored Mar 25, 2020
  f631b9dc
- OpenMP] Adding InaccessibleMemOnly and InaccessibleMemOrArgMemOnly for runtime calls. · 72b51d6f
  sstefan1 authored Mar 25, 2020
  72b51d6f
- [AArch64][SVE] Add SVE intrinsics for masked loads & stores · 05606329
  Kerry McLaughlin authored Mar 25, 2020
  05606329
- Rename test name, add more tests for codegenprepare · d82c1e8c
  Juneyoung Lee authored Mar 25, 2020
  
  d82c1e8c
- [ARM,MVE] Add missing tests for vqdmlash intrinsics. · 8f1651cc
  Simon Tatham authored Mar 25, 2020
  8f1651cc
- Add freeze(and x, const) case to codegenprepare's freeze-cmp.ll · e951a489
  Juneyoung Lee authored Mar 25, 2020
  
  e951a489
- [X86] Split masked instruction tests to enable D60940. · 2093fdd4
  Craig Topper authored Mar 24, 2020
  2093fdd4