Commits · 2faacf61a50e7f23fd10927cbbb98c59799bfcd0 · Roger Ferrer / llvm-epi · GitLab

Jun 24, 2022
- [SLP]Improve shuffles cost estimation where possible. · 2faacf61
  Alexey Bataev authored Dec 09, 2021
  2faacf61
- [GlobalOpt] Perform store->dominated load forwarding for stored once globals · e422c0d3
  Arthur Eubanks authored Jun 18, 2022
  e422c0d3
- [RISCV] Split a vectorizer test runline so that upcoming changes in defaults are visible · 056d6393
  Philip Reames authored Jun 24, 2022
  
  056d6393
- [RISCV] Modify a test line so it exercises the intended configuration once we... · adbe7186
  Philip Reames authored Jun 24, 2022
  adbe7186
- [AMDGPU] gfx11 VOPD instructions MC support · 07b7fada
  Joe Nash authored May 25, 2022
  07b7fada
- [RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]). · 78a31bb9
  Craig Topper authored Jun 24, 2022
  78a31bb9
- AMDGPU: Clear kill flags when optimizing vcmp save exec sequence · 7736ce1c
  Konstantin Zhuravlyov authored Jun 24, 2022
  7736ce1c
- [SelectionDAG][DAGCombiner] Reuse exist node by reassociate · 8c742056
  chenglin.bi authored Jun 24, 2022
  8c742056
- [InlineCost] Improve debugging experience by adding print about initial inlining cost · b7e7f4e1
  Dawid Jurczak authored Jun 24, 2022
  b7e7f4e1
- [GlobalOpt] Add tests for PR55859 (NFC) · 999aa6bf
  Nikita Popov authored Jun 24, 2022
  
  999aa6bf
- [SLP] Add cost model for `llvm.powi.*` intrinsics (REAPPLIED) · 0d417943
  Nabeel Omer authored Jun 22, 2022
  0d417943
- [AArch64] Convert vector add(ext, ext) into ext(add(ext, ext)) · 03c65c0d
  David Green authored Jun 24, 2022
  03c65c0d
- [BasicAA] Handle passthru calls in isEscapeSource() · bcadfc25
  Nikita Popov authored Jun 23, 2022
  bcadfc25
- [AArch64] Add addition extend of add/sub neon tests. NFC · ae7fbcd1
  David Green authored Jun 24, 2022
  
  ae7fbcd1
- [AArch64][SVE] Add sve.dupq.lane(insert(constant vector, 0), 0) ld1rq tests · cc3ef26f
  Matt Devereau authored Jun 24, 2022
  
  cc3ef26f
- Recommit "[ConstraintElimination] Transfer info from ULT to signed system." · 92f87787
  Florian Hahn authored Jun 24, 2022
  92f87787
- [RISCV] Move vfma_vl+fneg_vl matching to DAG combine. · c579ab53
  Craig Topper authored Jun 23, 2022
  c579ab53
- [GuardWidening] Update all tests with update_test_checks.py · 9ffe1b0a
  Serguei Katkov authored Jun 24, 2022
  
  9ffe1b0a
- [MachineSink] Clear kill flags on operands outside loop · 874fbe2c
  Carl Ritson authored Jun 24, 2022
  874fbe2c
- [PowerPC][AIX] Fix assertion message on AIX. NFC. · 106657df
  Kai Luo authored Jun 24, 2022
  106657df
- [PowerPC] Allow llvm.ppc.cfence to accept pointer types · 6710b21d
  Kai Luo authored Jun 24, 2022
  6710b21d
- [SelectionDAG] Enable WidenVecOp_VECREDUCE for scalable vector · 770fe864
  Lian Wang authored Jun 21, 2022
  770fe864
- Revert "[LoopInterchange] New cost model for loop interchange" · 878309cc
  Evgenii Stepanov authored Jun 23, 2022
  878309cc
Jun 23, 2022
- [WebAssembly][Object] Remove requirement that objects must have code sections · 5a082d9c
  Derek Schuff authored Jun 17, 2022
  5a082d9c
- [LoopInterchange] New cost model for loop interchange · 1b24fe34
  Congzhe Cao authored Jun 23, 2022
  1b24fe34
- [LV] Avoid a crash when costing a uniform store which doesn't correspond to a legal scatter · 46ea4b5e
  Philip Reames authored Jun 23, 2022
  46ea4b5e
- [SLP]Fix a crash when reorder masked gather nodes with reused scalars. · 3b6edef1
  Alexey Bataev authored Jun 22, 2022
  3b6edef1
- [Inline] Introduce a backend option to suppress inlining of functions with large stack sizes. · c50e6f59
  Wolfgang Pieb authored Jun 22, 2022
  c50e6f59
- [RISCV] Fix a crash in InsertVSETVLI where we hadn't properly guarded for a... · 1cc97922
  Philip Reames authored Jun 23, 2022
  1cc97922
- [test][GlobalOpt] Update precommitted test · b257acd2
  Arthur Eubanks authored Jun 23, 2022
  
  b257acd2
- [BasicTTI] Avoid crash when costing scalable select expansion · 0c132674
  Philip Reames authored Jun 23, 2022
  0c132674
- [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f. · 8b10ffab
  Craig Topper authored Jun 23, 2022
  8b10ffab
- [RISCV] Add macrofusion infrastructure and one example usage. · 4045b62d
  Craig Topper authored Jun 23, 2022
  4045b62d
- [AMDGPU] gfx11 Select on Buffer Atomic FAdd Rtn type · ae72fee7
  Joe Nash authored Jun 20, 2022
  ae72fee7
- Revert "[ConstraintElimination] Transfer info from ULT to signed system." · 94ed2caf
  Florian Hahn authored Jun 23, 2022
  94ed2caf
- [ConstraintElimination] Transfer info from ULT to signed system. · 316e106f
  Florian Hahn authored Jun 23, 2022
  316e106f
- [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c · 6f27df50
  Bradley Smith authored Jun 17, 2022
  6f27df50
- [AMDGPU] Flush the vmcnt counter in loop preheaders when necessary · 79e77a9f
  Baptiste Saleil authored Jun 23, 2022
  79e77a9f
- Revert "[fastalloc] Support allocating specific register class in fastalloc" · 851a5efe
  Nico Weber authored Jun 23, 2022
  851a5efe
- [BasicAA] Add test for call incorrectly treated as escape source (NFC) · 8b6f69a4
  Nikita Popov authored Jun 23, 2022
  
  8b6f69a4