llvm-svn: 27634

Clean up and fix various logical ops issues.

llvm-svn: 27633

llvm-svn: 27632

llvm-svn: 27631

llvm-svn: 27630

llvm-svn: 27629

llvm-svn: 27628

llvm-svn: 27627

llvm-svn: 27626

llvm-svn: 27625

different types.

Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1.  This compiles:

typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
  *P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
  *P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
  *P3 = vec_abs((vector float)*P3);
}

to:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        vspltisw v0, -1
        vslw v0, v0, v0
        lvx v1, 0, r3
        vand v1, v1, v0
        stvx v1, 0, r3
        lvx v1, 0, r4
        vandc v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vandc v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

instead of (with two constant pool entries):

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        li r6, lo16(LCPI1_0)
        lis r7, ha16(LCPI1_0)
        li r8, lo16(LCPI1_1)
        lis r9, ha16(LCPI1_1)
        lvx v0, r7, r6
        lvx v1, 0, r3
        vand v0, v1, v0
        stvx v0, 0, r3
        lvx v0, r9, r8
        lvx v1, 0, r4
        vand v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vand v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

GCC produces (with 2 cp entries):

_test:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc00c
        mtspr 256,r0
        lis r2,ha16(LC0)
        lis r9,ha16(LC1)
        la r2,lo16(LC0)(r2)
        lvx v0,0,r3
        lvx v1,0,r5
        la r9,lo16(LC1)(r9)
        lwz r12,-4(r1)
        lvx v12,0,r2
        lvx v13,0,r9
        vand v0,v0,v12
        stvx v0,0,r3
        vspltisw v0,-1
        vslw v12,v0,v0
        vandc v1,v1,v12
        stvx v1,0,r5
        lvx v0,0,r4
        vand v0,v0,v13
        stvx v0,0,r4
        mtspr 256,r12
        blr

llvm-svn: 27624

even though its not being built currently. This prevents dist-check from
failing because configure can't find llvm-config.in.in

llvm-svn: 27623

llvm-svn: 27622

a -L option to gccld whenever we're building a bytecode module or archive.
This gets around the "Cannot find library 'crtend'" warning messages.

llvm-svn: 27621

aggressive in some cases where LLVMGCC 4 is inserting casts for no reason.

This implements InstCombine/cast.ll:test27/28.

llvm-svn: 27620

llvm-svn: 27619

llvm-svn: 27618

llvm-svn: 27617

target .td file instead of adding SDNodes etc.

llvm-svn: 27616

llvm-svn: 27615

Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively.  This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI

llvm-svn: 27614

llvm-svn: 27613

llvm-svn: 27612

llvm-svn: 27611

Make this test more interesting by checking that the 0.0 used to implement vector fmul gets cse'd also.

llvm-svn: 27610

each other.  This implements CodeGen/PowerPC/vxor-canonicalize.ll

llvm-svn: 27609

llvm-svn: 27608

for SDOperand. This gets rid of numerous warnings in lib/CodeGen and
lib/Target when compiled with GCC 4.0.2

llvm-svn: 27607

llvm-svn: 27606

llvm-svn: 27605

Implement support for the formal_arguments node.  To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload

llvm-svn: 27604

llvm-svn: 27603

getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll

llvm-svn: 27602

llvm-svn: 27601

a distribution should need to be able to make a distribution so eliminate
the "make dist" from the list of targets attempted.

llvm-svn: 27600

__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.

llvm-svn: 27599

llvm-svn: 27598

Attribute John as an author.

llvm-svn: 27597

llvm-svn: 27596

Changed the order of operations so that more of the fine tuning is
performed in the release branch.  This should free up mainline sooner to
resume development.
Removed information on the special release Makefile targets as I've never
used them for a release; Tanya is investigating their integration, and they
can be re-added if she uses them.
Added an outline for building the LLVM GCC binary distributions.  I will
be filling that section out later (but before the 1.7 release).

llvm-svn: 27595