llvm-svn: 162722

llvm-svn: 162714

It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.

Atomic loads are also prevented from participating in rematerialization
and load folding.

llvm-svn: 162713

llvm-svn: 162707

Fix compile error when building with C++11 - clang thinks that PRIx64 is a user-defined suffix or something

llvm-svn: 162704

<rdar://problem/12183003>

llvm-svn: 162703

intended functionality change. Thanks to Ahmed Charles for spotting it.

llvm-svn: 162686

llvm-svn: 162678

llvm-svn: 162677

llvm-svn: 162672

The patch reviewed by Akira Hatanaka.

llvm-svn: 162668

llvm-svn: 162667

llvm-svn: 162665

llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was incompatible on i686 and Windows x64.

llvm-svn: 162664

llvm-svn: 162661

llvm-svn: 162660

llvm-svn: 162659

Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur.

llvm-svn: 162658

This section (introduced in DWARF-3) is used to define instruction address
ranges for functions that are not contiguous and can't be described
by low_pc/high_pc attributes (this is the usual case for inlined subroutines).
The patch is the first step to support fetching complete inlining info from DWARF.

Reviewed by Benjamin Kramer.

llvm-svn: 162657

Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1'

llvm-svn: 162656

FMA3 tests on bdver2 target for changes made in rev 162012. Also made
corresponding changes to existing tests for darwin triple to ensure that
same pattern is tested for bdver2 target.

llvm-svn: 162655

Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.

llvm-svn: 162654

llvm-svn: 162653

--as-needed.
Patch by Felix Geyer. Fixes pr13262.

llvm-svn: 162652

llvm-svn: 162649

Reviewed offline by chandlerc.

llvm-svn: 162623

llvm-svn: 162622

ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.

llvm-svn: 162615

Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

llvm-svn: 162614

It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.

This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.

llvm-svn: 162603

Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

llvm-svn: 162599

The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.

The argument registers should be added as implicit uses.

llvm-svn: 162593

There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.

llvm-svn: 162592

It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.

llvm-svn: 162591

llvm-svn: 162589

second operand is MipsISD::GPRel.

llvm-svn: 162584

llvm-svn: 162578

ProfileDataTypes.h header.

With this patch the old and new profiling code can exist side-by-side. The new
profiling code will be submitted soon and it only supports insert-edge-profiling
for now and will not depend on ProfileInfo.

Patch by Alastair Murray.

llvm-svn: 162576

the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.

llvm-svn: 162572

It is now allowed to explicitly set hasSideEffects, mayStore, and
mayLoad on instructions with patterns.

Verify that the patterns are consistent with the explicit flags.

llvm-svn: 162569