Commits · 3ca6dea05dec44680f29a40de7481aede09cae8a · Roger Ferrer / llvm-epi · GitLab

Jul 26, 2021
- [libc++][NFC] Change a few instances of > > to >> in C++20 code · 3ca6dea0
  Louis Dionne authored Jul 26, 2021
  
  3ca6dea0
- [SimplifyLibCalls] avoid crash on pointer math · 87d604ff
  Sanjay Patel authored Jul 26, 2021
  87d604ff
- [SimplifyLibCalls] reduce code duplication; NFC · d8260269
  Sanjay Patel authored Jul 26, 2021
  
  d8260269
- [MergeICmps] Separate out BCECmp and use Optional (NFC) · 0d3807b3
  Nikita Popov authored Jul 26, 2021
  0d3807b3
- [LV] Don't assume isScalarAfterVectorization if one of the uses needs widening. · 981e9dce
  Sander de Smalen authored Jul 26, 2021
  981e9dce
- [AArch64][SVE] Break false dependencies for inactive lanes of unary operations · 81eafb8a
  Bradley Smith authored Jul 08, 2021
  81eafb8a
- [Clang][OpenMP] Remove the mandatory flush for capture for OpenMP 5.1 · 3274cdc8
  Shilei Tian authored Jul 26, 2021
  3274cdc8
- [SystemZ] Add support for new cpu architecture - arch14 · 8cd8120a
  Ulrich Weigand authored Jul 20, 2021
  8cd8120a
- Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit." · 7a1e73f0
  Florian Hahn authored Jul 26, 2021
  7a1e73f0
- [libc++][ci] Detect not committed generated files. · 1139fd42
  Mark de Wever authored Jul 22, 2021
  1139fd42
- [IR] Consider non-willreturn as side effect (PR50511) · 33146857
  Nikita Popov authored Jul 21, 2021
  33146857
- Simplify away some SmallVector copies. NFCI. · 404f0d4f
  Benjamin Kramer authored Jul 26, 2021
  404f0d4f
- [Analyzer][solver][NFC] print constraints deterministically (ordered by their... · 4761321d
  Gabor Marton authored Jul 20, 2021
  4761321d
- [InstrRef][AArch64][1/4] Accept constant physreg variable locations · f86694cb
  Jeremy Morse authored Jul 26, 2021
  f86694cb
- [LV] Add test to store a first-order rec via interleave group. · 93664503
  Florian Hahn authored Jul 26, 2021
  93664503
- [SLP]Fix costs calculations. · 6ca48efc
  Alexey Bataev authored Jul 26, 2021
  6ca48efc
- [OpenCL] Change default standard version to CL1.2 · 81600160
  Anastasia Stulova authored Jul 26, 2021
  81600160
- [llvm-readobj] Display multiple function names for stack size entries · 87ed73fe
  gbreynoo authored Jul 26, 2021
  87ed73fe
- [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset · 59f68652
  Jay Foad authored Jul 21, 2021
  59f68652
- [AMDGPU] Pre-commit global-isel test case for D106451 · 683b9ed0
  Jay Foad authored Jul 21, 2021
  683b9ed0
- [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset · 9ac10658
  Jay Foad authored Jul 19, 2021
  9ac10658
- [ARM] Ensure correct regclass in distributing postinc · 010f8e30
  David Green authored Jul 26, 2021
  010f8e30
- AArch64: support i128 (& larger) returns in GlobalISel · a487a49a
  Tim Northover authored Jul 26, 2021
  
  a487a49a
- [SimplifyCFG] Improve store speculation check · ffb3277b
  Nikita Popov authored Jul 21, 2021
  ffb3277b
- [SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths · e484e1ae
  Kerry McLaughlin authored Jul 26, 2021
  e484e1ae
- Revert "[SLP]Fix costs calculations." · d7cb2a07
  Alexey Bataev authored Jul 26, 2021
  d7cb2a07
- [AArch65][SVE] Remove vector_splice from AddedComplexity pattern · bf28111e
  Caroline Concatto authored Jul 26, 2021
  bf28111e
- [mlir] split type conversion to two lines for GCC's sake · 539437e2
  Tres Popp authored Jul 26, 2021
  
  539437e2
- [SLP]Fix costs calculations. · a053afed
  Alexey Bataev authored Jul 22, 2021
  a053afed
- [NFC] Change VFShape so it contains an ElementCount rather than seperate VF... · 8a8d01d5
  Paul Walker authored Jul 24, 2021
  8a8d01d5
- [Inliner] Make the CallPenalty configurable · 46c03668
  Philipp Krones authored Jul 14, 2021
  46c03668
- [VPlan] Use stored value from recipes for interleave groups. · d995d637
  Florian Hahn authored Jul 26, 2021
  d995d637
- [SVE] Add support for folding for select + masked loads · 20b0fa91
  Dylan Fleming authored Jul 26, 2021
  20b0fa91
- [SVE][AArch64] Improve code generation for vector_splice for Imm > 0 · 0bfc26e3
  Caroline Concatto authored Jul 19, 2021
  0bfc26e3
- Fix test failures caused by 0aff1798 · b2a5f002
  David Sherwood authored Jul 26, 2021
  
  b2a5f002
- [AArch64][SVE] Improve code generation for vector_splice for Imm == -1 · 73e4e9cd
  Caroline Concatto authored Jul 06, 2021
  73e4e9cd
- [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets · c8472db0
  Simon Pilgrim authored Jul 26, 2021
  c8472db0
- [X86][SSE] Don't scrub address math from interleaved shuffle tests · f64e2515
  Simon Pilgrim authored Jul 26, 2021
  
  f64e2515
- Revert "[clangd] Avoid range-loop init-list lifetime subtleties." · e9274af7
  Sam McCall authored Jul 26, 2021
  e9274af7
- [AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc() · e6ff9179
  Cullen Rhodes authored Jul 26, 2021
  e6ff9179