Commits · 4ff2f60f1fdaadebafc2daa8fef77ed331545904 · Roger Ferrer / llvm-epi · GitLab

Sep 27, 2023
- [RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419) · aff6ffc8
  Luke Lau authored Sep 27, 2023
  aff6ffc8
- CostModel/RISCV: tweak cost of vector ctpop under ZVBB (#67020) · 7c128f6d
  Ramkumar Ramachandra authored Sep 27, 2023
  7c128f6d
- [RISCV][CostModel] Estimate cost of Extract/InsertElement with non-constant... · 3d7df0a5
  Sergey Kachkov authored Sep 27, 2023
  3d7df0a5
- [RISCV] Remove duplicate pattern in RISCVInstrInfoVPseudos.td (#67436) · 2153eb37
  Brandon Wu authored Sep 27, 2023
  
  2153eb37
- [RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin · 5278cc36
  Jianjian GUAN authored Aug 29, 2023
  5278cc36
- [RISCV] Support fmaximum/fminimum for fp16 vector when only Zvfhmin enabled (#67393) · d6b1b998
  Jim Lin authored Sep 27, 2023
  d6b1b998
- [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866) · 435da4ef
  Jianjian GUAN authored Sep 27, 2023
  435da4ef
- [RISCV] Remove unused isSEWAware, NFC (#67411) · abd0fab1
  Jianjian GUAN authored Sep 27, 2023
  
  abd0fab1
Sep 26, 2023
- [RISCV] Correct Zhinx load/store patterns to use AddrRegImm. · b26157ed
  Craig Topper authored Sep 26, 2023
  
  b26157ed
- [RISCV] Disable constant hoisting for mul by one more/less than a pow… (#67385) · 64b1fbb3
  Craig Topper authored Sep 26, 2023
  64b1fbb3
- [RISCV] Update comment on -w stripping pass. NFC (#67415) · 733e3c60
  Luke Lau authored Sep 26, 2023
  733e3c60
- [RISCV] Explicitly create IMPLICIT_DEF instead of UNDEF for vectors i… (#67369) · 65eb4687
  Craig Topper authored Sep 26, 2023
  65eb4687
- [RISCV] Transform build_vector((binop X_i, C_i)..) to binop (build_vector, build_vector) (#67358) · e39add89
  Philip Reames authored Sep 26, 2023
  e39add89
- [RISCV] Add searchable table for tune information (#66193) · 08165c44
  Pengcheng Wang authored Sep 26, 2023
  08165c44
- [RISCV][GISel] Add RegBank selection for G_SMULH (#67381) · de17384c
  Min-Yih Hsu authored Sep 25, 2023
  de17384c
- [RISCV][GISel] Add instruction selection for G_SEXT, G_ZEXT, and G_SEXT_INREG (#67359) · 0d7c340c
  Min-Yih Hsu authored Sep 25, 2023
  0d7c340c
Sep 25, 2023
- [RISCV] Don't set KILL flag on X0 in RISCVInstrInfo::movImm. · 62f56368
  Craig Topper authored Sep 25, 2023
  62f56368
- [TargetLowering] Deduplicate choosing InlineAsm constraint between ISels (#67057) · 330fa7d2
  Nick Desaulniers authored Sep 25, 2023
  330fa7d2
- [RISCV] Be more aggressive about shrinking constant build_vector etype (#67175) · 95ce3c23
  Philip Reames authored Sep 25, 2023
  95ce3c23
- [RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599) · 0a5d52a7
  Sergey Kachkov authored Sep 25, 2023
  0a5d52a7
- [RISCV] Support floating point VCIX (#67094) · 408b0810
  Brandon Wu authored Sep 25, 2023
  
  408b0810
- [RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613) · 7c70e50b
  Yeting Kuo authored Sep 25, 2023
  7c70e50b
Sep 23, 2023
- [RISCV][GISel] Emit G_CONSTANT 0 as a copy from X0. (#67202) · 972df2ce
  Craig Topper authored Sep 22, 2023
  972df2ce
Sep 22, 2023
- [RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL fold · 233b6ef6
  Philip Reames authored Sep 22, 2023
  233b6ef6
- [RISCV][GISel] Implement instruction selection for G_PHI and G_BRCOND. · 98eb28b6
  Craig Topper authored Sep 20, 2023
  98eb28b6
- [RISCV] Ruse an existing variable to shorten a line [nfc] · b38f31ae
  Philip Reames authored Sep 22, 2023
  
  b38f31ae
- [RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value of PseudoFloatLoad (#67014) · 079b8bae
  Pengcheng Wang authored Sep 23, 2023
  079b8bae
- [RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053) · 8e87dc10
  Craig Topper authored Sep 22, 2023
  8e87dc10
- [RISCV] Truncate constants to eltwidth before checking simm5 when con… (#67062) · ec5b0ef7
  Craig Topper authored Sep 22, 2023
  ec5b0ef7
- [RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037) · 3510552d
  Luke Lau authored Sep 22, 2023
  3510552d
Sep 21, 2023
- ISel/RISCV: remove dead code corresponding to VP_FSH[L|R] (#67035) · 3b3ff5c1
  Ramkumar Ramachandra authored Sep 21, 2023
  3b3ff5c1
- [RISCV] Shrink vslideup's LMUL when lowering fixed insert_subvector (#65997) · b5ff71e2
  Luke Lau authored Sep 21, 2023
  b5ff71e2
- [RISCV] Add overlapping constraints label · 13e9a568
  Piyou Chen authored Sep 20, 2023
  13e9a568
- Recommmit "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)" · cbd45961
  Craig Topper authored Sep 20, 2023
  cbd45961
- Revert "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)" · ea064ba6
  Craig Topper authored Sep 20, 2023
  ea064ba6
- [RISCV] Improve contant materialization to end with 'not' if the cons… (#66950) · a8b8e947
  Craig Topper authored Sep 20, 2023
  a8b8e947
Sep 20, 2023
- [RISCV] Fix bugs about register list of Zcmp push/pop. (#66073) · 976df42e
  Yeting Kuo authored Sep 20, 2023
  976df42e
- [RISCV] Prefer Zcmp push/pop instead of save-restore calls. (#66046) · ab94fbba
  Yeting Kuo authored Sep 20, 2023
  ab94fbba
Sep 19, 2023
- [RISCV] Match strided load via DAG combine (#66800) · 86b32c4b
  Philip Reames authored Sep 19, 2023
  86b32c4b
- [RISCV] Require alignment when forming gather with larger element type · fc95de38
  Philip Reames authored Sep 19, 2023
  fc95de38