- Jun 17, 2015
-
-
Toma Tabacu authored
Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10497 llvm-svn: 239899
-
Toma Tabacu authored
Summary: Previously, MCSymbolRefExpr::create() was called with a StringRef of the symbol name, which it would then search for in the Symbols StringMap (from MCContext). However, relative labels (which are temporary symbols) are apparently not stored in the Symbols StringMap, so we end up creating a new {$,.L}tmp symbol ({$,.L}tmp00, {$,.L}tmp10 etc.) each time we create an MCSymbolRefExpr by passing in the symbol name as a StringRef. Fortunately, there is a version of MCSymbolRefExpr::create() which takes an MCSymbol* and we already have an MCSymbol* at that point, so we can just pass that in instead of the StringRef. I also removed the local StringRef calls to MCSymbolRefExpr::create() from expandMemInst(), as those cases can be handled by evaluateRelocExpr() anyway. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9938 llvm-svn: 239897
-
- Jun 16, 2015
-
-
Daniel Sanders authored
Summary: Relocs that can be converted from absolute to PC-relative now do so if IsPCRel is true. Relocs that require PC-relative now call llvm_unreachable() if IsPCRel is false and similarly those that require absolute assert that IsPCRel is false. Note that while it looks like some relocs (e.g. R_MIPS_26) can be converted into the MIPS32r6/MIPS64r6 relocs (R_MIPS_PC*_S2), it isn't actually valid to do so. Placeholders have been left in the testcase for unsupported relocs and relocs that cannot be generated at the moment. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D10184 llvm-svn: 239817
-
- Jun 11, 2015
-
-
Toma Tabacu authored
Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
-
Zoran Jovanovic authored
http://reviews.llvm.org/D10091 llvm-svn: 239522
-
Zoran Jovanovic authored
http://reviews.llvm.org/D10312 llvm-svn: 239520
-
- Jun 09, 2015
-
-
Toma Tabacu authored
Specified the llvm namespace for the 2 calls to make_unique() which caused compilation errors in Visual Studio 2013. llvm-svn: 239405
-
Toma Tabacu authored
It was breaking buildbots. llvm-svn: 239397
-
Toma Tabacu authored
Summary: For some branches, GAS accepts an immediate instead of the 2nd register operand. We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9666 llvm-svn: 239396
-
- Jun 05, 2015
-
-
Toma Tabacu authored
This is breaking the Windows buildbots. llvm-svn: 239145
-
Toma Tabacu authored
Summary: Only restoring AvailableFeatures is not enough and will lead to buggy behaviour. For example, if we have a feature enabled and we ".set pop", the next time we try to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])" check will be false, because we didn't restore STI.FeatureBits. In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop". This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits, but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits). I also moved the updating of AssemblerOptions inside the "if" statement in setFeatureBits() and clearFeatureBits(), as there is no reason to update if nothing changes. Reviewers: dsanders, mkuper Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9156 llvm-svn: 239144
-
- Jun 04, 2015
-
-
Rafael Espindola authored
llvm-svn: 239041
-
- Jun 02, 2015
-
-
Toma Tabacu authored
Summary: Make mips-expansions.s more readable by grouping the instructions with their respective CHECK's. This test is going to get a lot bigger soon and it will become essentially unreadable if the current formatting is kept. I've also made the comments more useful and accurate, and I've restricted the RUN lines to under 80 columns. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10089 llvm-svn: 238817
-
Daniel Sanders authored
The second %dtprel_hi is used on an addiu so it looks like a copy/paste error. llvm-svn: 238815
-
Daniel Sanders authored
llvm-svn: 238814
-
Toma Tabacu authored
Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
-
- Jun 01, 2015
-
-
Rafael Espindola authored
This handles only the 32 bit case. llvm-svn: 238751
-
- May 28, 2015
-
-
Kai Nacke authored
Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
-
- May 27, 2015
-
-
Zoran Jovanovic authored
Differential Revision: http://reviews.llvm.org/D9739 llvm-svn: 238333
-
Jozef Kolek authored
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions using mapping. Differential Revision: http://reviews.llvm.org/D10031 llvm-svn: 238325
-
- May 22, 2015
-
-
Rafael Espindola authored
It is not relevant where in the string table the name is located. llvm-svn: 238053
-
- May 21, 2015
-
-
Toma Tabacu authored
llvm-svn: 237884
-
- May 19, 2015
-
-
Zoran Jovanovic authored
Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
-
Zoran Jovanovic authored
Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
-
Zoran Jovanovic authored
Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
-
Jozef Kolek authored
This patch implements LSA instruction using mapping. Differential Revision: http://reviews.llvm.org/D8919 llvm-svn: 237634
-
- May 18, 2015
-
-
Jozef Kolek authored
This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
-
- May 15, 2015
-
-
Toma Tabacu authored
Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
-
- May 14, 2015
-
-
Toma Tabacu authored
Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9564 llvm-svn: 237366
-
Toma Tabacu authored
Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
-
Toma Tabacu authored
Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
-
- May 13, 2015
-
-
Jozef Kolek authored
This patch implements CLO and CLZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8553 llvm-svn: 237257
-
Toma Tabacu authored
Summary: A side-effect of this is that LA gains proper handling of unsigned and positive signed 16-bit immediates and more accurate error messages. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9290 llvm-svn: 237255
-
Toma Tabacu authored
Summary: Also did some minor reformatting in the resulting test. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9702 llvm-svn: 237242
-
- May 12, 2015
-
-
Jozef Kolek authored
This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
-
- May 08, 2015
-
-
Jozef Kolek authored
This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 llvm-svn: 236858
-
Jozef Kolek authored
This patch implements ADDIUPC and LWPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8415 llvm-svn: 236852
-
- May 07, 2015
-
-
Jozef Kolek authored
This patch implements JIALC and JIC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8389 llvm-svn: 236748
-
Toma Tabacu authored
Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
-
- May 05, 2015
-
-
Daniel Sanders authored
Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
-