Commits · 79dc4420f0106dbc466f00d806484adc9aa8c630 · Roger Ferrer / llvm-epi · GitLab

Oct 01, 2014
- [mips] For indirect calls we don't need $gp to point to .got. Mips linker · 7072a796
  Sasa Stankovic authored Oct 01, 2014
  7072a796
- [x86] Teach the new vector shuffle lowering to be even more aggressive · 26cb9b8d
  Chandler Carruth authored Oct 01, 2014
  26cb9b8d
- [x86] Hoist the zext-lowering up in the v4i32 lowering routine -- it is · 846baf2c
  Chandler Carruth authored Oct 01, 2014
  846baf2c
- [x86] Teach the new vector shuffle lowering about VBROADCAST and · b9d3fa1e
  Chandler Carruth authored Oct 01, 2014
  b9d3fa1e
- [x86] Add AVX1 and AVX2 testing to all of the 128-bit shuffle test · bebedbaf
  Chandler Carruth authored Sep 30, 2014
  bebedbaf
- [x86] Update the exact FileCheck syntax of the 256-bit and 512-bit · a41dceb3
  Chandler Carruth authored Sep 30, 2014
  a41dceb3
Sep 30, 2014
- [x86] Rework all of the 128-bit vector shuffle tests with my handy test · 6a62cd35
  Chandler Carruth authored Sep 30, 2014
  6a62cd35
- Recommit r218010 [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ. · c110c0b9
  Juergen Ributzka authored Sep 30, 2014
  c110c0b9
- R600/SI: Fix printing of clamp and omod · 97069780
  Matt Arsenault authored Sep 30, 2014
  97069780
- Add numeric extend, trunctate to mips fast-isel · 3ebdcc9e
  Reed Kotler authored Sep 30, 2014
  3ebdcc9e
- [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}. · 28a7df0b
  Robert Khasanov authored Sep 30, 2014
  28a7df0b
- [AVX512] Added intrinsics for 128- and 256-bit versions of VCMPEQ{BWDQ} · 5aa4445b
  Robert Khasanov authored Sep 30, 2014
  5aa4445b
- [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW. · b25e562d
  Robert Khasanov authored Sep 30, 2014
  b25e562d
- [AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ. · a27c8e0f
  Robert Khasanov authored Sep 30, 2014
  a27c8e0f
- [x86] Revert r218588, r218589, and r218600. These patches were pursuing · aaf8e03d
  Chandler Carruth authored Sep 30, 2014
  aaf8e03d
- [x86] Add some vector-register broadcast operations to the 256-bit v4 · 964747ad
  Chandler Carruth authored Sep 30, 2014
  964747ad
- R600: Fix broken check lines, missing scalar case. · 1c4571e0
  Matt Arsenault authored Sep 30, 2014
  1c4571e0
- [FastISel][AArch64] Fold sign-/zero-extends into the load instruction. · 6ac12439
  Juergen Ributzka authored Sep 30, 2014
  6ac12439
Sep 29, 2014
- Add soft-float to the key for the subtarget lookup in the TargetMachine · 6a0551e4
  Eric Christopher authored Sep 29, 2014
  6a0551e4
- R600/SI: Also fix fsub + fadd a, a to mad combines · 3d4233fe
  Matt Arsenault authored Sep 29, 2014
  3d4233fe
- R600/SI: Fix using mad with multiplies by 2 · 02cb0ff7
  Matt Arsenault authored Sep 29, 2014
  02cb0ff7
- [x86] Make the new vector shuffle lowering lower blends as VSELECT · 6cbf4316
  Chandler Carruth authored Sep 29, 2014
  6cbf4316
- [x86] Delete a bunch of really bad and totally unnecessary code in the · b1cc7a85
  Chandler Carruth authored Sep 29, 2014
  b1cc7a85
- [x86] Add the dispatch skeleton to the new vector shuffle lowering for · c7129276
  Chandler Carruth authored Sep 29, 2014
  c7129276
- [x86] Teach the new vector shuffle lowering to fall back on AVX-512 · 24e3b69c
  Chandler Carruth authored Sep 28, 2014
  24e3b69c
- [x86] Fix the new vector shuffle lowering's use of VSELECT for AVX2 · abe742e8
  Chandler Carruth authored Sep 28, 2014
  abe742e8
Sep 28, 2014
- [x86] Fix a really silly bug that I introduced fixing another bug in the · 6578f920
  Chandler Carruth authored Sep 28, 2014
  6578f920
- [x86] Fix yet another bug in the new vector shuffle lowering's handling · b10c6b8e
  Chandler Carruth authored Sep 28, 2014
  b10c6b8e
Sep 27, 2014
- [AArch64] Redundant store instructions should be removed as dead code · 463db9a7
  James Molloy authored Sep 27, 2014
  463db9a7
- [x86] Fix terrible bugs everywhere in the new vector shuffle lowering · 4d03be17
  Chandler Carruth authored Sep 27, 2014
  4d03be17
- [x86] Flip the sentinel values used in the target shuffle mask decoding · 81e6b29f
  Chandler Carruth authored Sep 27, 2014
  81e6b29f
- Refactor reciprocal and reciprocal square root estimate into target-independent functions (part 2). · bdf1e388
  Sanjay Patel authored Sep 26, 2014
  bdf1e388
Sep 26, 2014
- [x86] Fix a moderately terrifying bug in the new 128-bit shuffle logic · f572f3b2
  Chandler Carruth authored Sep 26, 2014
  f572f3b2
- R600/SI: Add strict check lines to div_scale tests. · ed8a3e0a
  Matt Arsenault authored Sep 26, 2014
  ed8a3e0a
- R600/SI Allow same SGPR to be used for multiple operands · 6a0919fb
  Matt Arsenault authored Sep 26, 2014
  6a0919fb
- R600/SI: Partially move operand legalization to post-isel hook. · cb0ac3d1
  Matt Arsenault authored Sep 26, 2014
  cb0ac3d1
- R600/SI: Don't move operands that are required to be SGPRs · 5885bef6
  Matt Arsenault authored Sep 26, 2014
  5885bef6
- R600/SI: Fix using wrong operand indices when commuting · aff65fbc
  Matt Arsenault authored Sep 26, 2014
  aff65fbc
- [x86] In the new vector shuffle lowering, when trying to do another · 0c9ee10d
  Chandler Carruth authored Sep 26, 2014
  0c9ee10d
- [x86] Fix a large collection of bugs that crept in as I fleshed out the · 5afd4c26
  Chandler Carruth authored Sep 26, 2014
  5afd4c26