Commits · 95291a0e34c74d9be0ad216465a2a2e9db9610d4 · Roger Ferrer / llvm-epi · GitLab

Feb 24, 2020
- [Hexagon] Lower bitcast of a vector predicate · a8a4f99a
  Ikhlas Ajbar authored Jan 09, 2020
  a8a4f99a
- [X86] Add back fmaddsub intrinsics to work towards fixing the strict fp implementation · 72732843
  Craig Topper authored Feb 24, 2020
  72732843
- [AMDGPU] use llvm_unreachable instead of default for rp set · 4135077e
  Stanislav Mekhanoshin authored Feb 23, 2020
  4135077e
- [AVR] Disassemble register operands · 5b2046c9
  Ayke van Laethem authored Feb 05, 2020
  5b2046c9
- [X86] combineX86ShuffleChain - select X86ISD::FAND/ISD::AND based on MaskVT · daac8dba
  Simon Pilgrim authored Feb 24, 2020
  daac8dba
- [AVR] Don't assert on an undefined operand · d1af6011
  Ayke van Laethem authored Feb 04, 2020
  d1af6011
- [AVR] Use correct register class for mul instructions · a5424ded
  Ayke van Laethem authored Feb 24, 2020
  a5424ded
- [XCOFF][AIX] Fix incorrect alignment for function descriptor csect · bee70bff
  jasonliu authored Feb 24, 2020
  bee70bff
- [X86] getTargetShuffleInputs - check that the source inputs are all the right size. · 59d8d13c
  Simon Pilgrim authored Feb 24, 2020
  59d8d13c
- [PowerPC][AIX] Spill/restore the callee-saved condition register bits. · 8efc2f57
  Sean Fertile authored Feb 24, 2020
  8efc2f57
- [CostModel][X86] We don't need a scale factor for SLM extract costs · b8243887
  Simon Pilgrim authored Feb 24, 2020
  b8243887
- [MIR][ARM] MachineOperand comments · 7efabe5c
  Sjoerd Meijer authored Feb 24, 2020
  7efabe5c
- [AArch64][SVE] Add the SVE dupq_lane intrinsic · f87f23c8
  Kerry McLaughlin authored Feb 24, 2020
  f87f23c8
- [RDA][ARM][LowOverheadLoops] Iteration count IT blocks · a67eb221
  Sam Parker authored Feb 24, 2020
  a67eb221
- [AArch64][SVE] Add intrinsics for SVE2 cryptographic instructions · f2ff1534
  Kerry McLaughlin authored Feb 24, 2020
  f2ff1534
- [MC] Widen the functional unit type from 32 to 64 bits. · c3f36acc
  Bevin Hansson authored Dec 09, 2019
  c3f36acc
- [ARM][MVE] Combine more extending masked loads · 03756a41
  Sam Parker authored Feb 21, 2020
  03756a41
- [X86] When creating X86ISD::MGATHER nodes from AVX2 gather intrinsics, cast... · 7a7146cf
  Craig Topper authored Feb 23, 2020
  7a7146cf
- [X86] Use custom isel for gather/scatter instructions. · f1b8ec33
  Craig Topper authored Feb 23, 2020
  f1b8ec33
- [NFC][PowerPC] Refactor the tryAndWithMask() · 8b3a62dc
  QingShan Zhang authored Feb 24, 2020
  8b3a62dc
- [X86] Remove most X86 specific subclasses of MemSDNode. Just use a... · 5a705186
  Craig Topper authored Feb 23, 2020
  5a705186
- [X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1. · 15b6aa74
  Craig Topper authored Feb 23, 2020
  15b6aa74
- [X86] Use FIST for i64 atomic stores on 32-bit targets without SSE. · 2a10f801
  Craig Topper authored Feb 23, 2020
  
  2a10f801
Feb 23, 2020
- [SystemZ] Support the kernel back chain. · 82879c29
  Jonas Paulsson authored Feb 19, 2020
  82879c29
- [X86] Add AddToWorklist(N) after calls to... · 84cd968f
  Craig Topper authored Feb 22, 2020
  84cd968f
- [X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD... · bdb1729c
  Craig Topper authored Feb 22, 2020
  bdb1729c
- [X86] Use movlps for i64 atomic stores on 32-targets with sse1. · e7a184fc
  Craig Topper authored Feb 22, 2020
  e7a184fc
Feb 22, 2020
- [VE][fix] missing include · 635034f1
  Simon Moll authored Feb 22, 2020
  
  635034f1
- [X86] Teach combineCVTPH2PS to shrink v8i16 loads when the output type is... · 228a2bc9
  Craig Topper authored Feb 21, 2020
  228a2bc9
- [WebAssembly] Fix a non-determinism problem in FixIrreducibleControlFlow · 3648370a
  Heejin Ahn authored Feb 21, 2020
  3648370a
- AMDGPU/GlobalISel: Remove dead code · bf4933b4
  Matt Arsenault authored Feb 18, 2020
  
  bf4933b4
- Revert "[AMDGPU] Don’t marke the .note section as ALLOC" · d3e170c4
  Mark Searles authored Feb 21, 2020
  d3e170c4
Feb 21, 2020
- [Target] Remove libObject dependency in lib/Target · a32d5397
  Francis Visoiu Mistrih authored Feb 21, 2020
  a32d5397
- [AArch64] Delete an unneeded dependency on Object after 1874dee5 · fddbff14
  Fangrui Song authored Feb 21, 2020
  fddbff14
- [AArch64][SVE] Fix -DBUILD_SHARED_LIBS=on builds after... · fad1c750
  Fangrui Song authored Feb 21, 2020
  fad1c750
- [AArch64][SVE] Fix -Wimplicit-fallthrough after D73711 · 5c33a81b
  Fangrui Song authored Feb 21, 2020
  
  5c33a81b
- [AArch64][SVE] Add support for DestructiveBinary and DestructiveBinaryComm DestructiveInstTypes · a5b22b76
  Cameron McInally authored Feb 21, 2020
  a5b22b76
- AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 · b72f1448
  Jay Foad authored Feb 21, 2020
  b72f1448
- [macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat · 1874dee5
  Francis Visoiu Mistrih authored Feb 18, 2020
  1874dee5
- [X86] Add a new format type for instructions that represent named prefix bytes... · 8875ee18
  Craig Topper authored Feb 21, 2020
  8875ee18