Commits · a8c24d57b81703b5730460d7cb12af9783a02539 · Roger Ferrer / llvm-epi · GitLab

Nov 07, 2022
- [AArch64][SVE2] Add the SVE2.1 BF16 instructions · cf69895a
  David Sherwood authored Nov 02, 2022
  cf69895a
- [X86] Folded MOVDDUPrm has the same sched behaviour as MOVSHDUPrm/MOVSLDUPrm on Haswell/IceLake · 5c0cb757
  Simon Pilgrim authored Nov 07, 2022
  5c0cb757
- [AArch64] Add SME2.1 target feature for Armv9-A 2022 Architecture Extension · 12a6572d
  David Sherwood authored Nov 03, 2022
  12a6572d
- [AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands · 8f689521
  Dmitry Preobrazhensky authored Nov 07, 2022
  8f689521
- [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16 · 6e279f5b
  Dmitry Preobrazhensky authored Nov 07, 2022
  6e279f5b
- [X86] Flatten WriteShift/Rotate SchedRW defs · 4aabbc0c
  Simon Pilgrim authored Nov 07, 2022
  4aabbc0c
- Recommit [AArch64] Improve codegen for shifted mask op · 83255c4a
  chenglin.bi authored Nov 07, 2022
  83255c4a
- [PowerPC] Use llvm::is_contained (NFC) · 7c2b76f7
  Kazu Hirata authored Nov 06, 2022
  
  7c2b76f7
Nov 06, 2022
- [X86] Schedule scalar movsx/movzx load+extend ops as WriteLoad instead of WriteALULd · 4e56aa25
  Simon Pilgrim authored Nov 06, 2022
  4e56aa25
- [X86] Fix scalar load latencies for WriteLoad scheduler class · 08fe55b3
  Simon Pilgrim authored Nov 06, 2022
  08fe55b3
- Revert rG244331ae833aaf33503bbd36890e704afb66a237 "[X86] Fix scalar load... · 6fff3bab
  Simon Pilgrim authored Nov 06, 2022
  6fff3bab
- [X86] Fix scalar load latencies for WriteLoad scheduler class · 244331ae
  Simon Pilgrim authored Nov 06, 2022
  244331ae
Nov 05, 2022
- [X86] Replace unnecessary int2float and float2double overrides with better base class defs · edf88553
  Simon Pilgrim authored Nov 05, 2022
  edf88553
- [X86] Cleanup WriteCvtSD2SS/WriteCvtPD2PS overrides · 2c79186b
  Simon Pilgrim authored Nov 05, 2022
  2c79186b
- [X86] Fix cvtss2si64/cvttss2si64 typo in SkylakeClient · 0b7f3278
  Simon Pilgrim authored Nov 05, 2022
  0b7f3278
- [X86] Fix override for CVTPD2PS/CVTPD2DQ/CVTTPD2DQ AVX variants · b781ca4d
  Simon Pilgrim authored Nov 05, 2022
  b781ca4d
- [X86] Add SchedWriteVecTruncate scheduler per-width wrapper · ee1ad1a6
  Simon Pilgrim authored Nov 05, 2022
  ee1ad1a6
- [X86] Add missing ReadAfterFold attributes from CVTSD2SSrm/CVTSS2SDrm to match... · 184817d0
  Simon Pilgrim authored Nov 05, 2022
  184817d0
- [X86] Remove SandyBridge CVTSS2SIrm/CVTSD2SIrm overrides · 1bd6471c
  Simon Pilgrim authored Nov 05, 2022
  1bd6471c
- [X86] Replace unnecessary int2double overrides with a better WriteCvtI2PD def · d95dc5bc
  Simon Pilgrim authored Nov 05, 2022
  d95dc5bc
- [RISCV] Add isel pattern for (and X, 0xffffffff << C) with Zba. · 91aa233b
  Craig Topper authored Nov 04, 2022
  91aa233b
- [RISCV] Remove duplicate SDNodeXForm. NFC · 0faac150
  Craig Topper authored Nov 04, 2022
  
  0faac150
- [RISCV] Rename isAllUsesReadW to hasAllWUsers in RISCVSExtWRemoval. NFC · d6b224ed
  Craig Topper authored Nov 04, 2022
  
  d6b224ed
- R600: Remove broken atomicrmw patterns · 026ddced
  Matt Arsenault authored Nov 03, 2022
  026ddced
Nov 04, 2022
- AMDGPU: Fold undef rcp to qnan · ada6aa3f
  Matt Arsenault authored Oct 16, 2022
  ada6aa3f
- AMDGPU: Fix assert when trying to overextend liverange · 09d38dd7
  Matt Arsenault authored Oct 24, 2022
  09d38dd7
- [LLVM][AMDGPU] Specialize 32-bit atomic fadd instruction for generic address space · 1186e9d5
  Shilei Tian authored Nov 04, 2022
  1186e9d5
- [RISCV] Define custom-N opcodes · 254bf678
  Philip Reames authored Nov 04, 2022
  254bf678
- [AMDGPU] Skip stack-arg dbg objects while fixing the dead frame indices · a8d7ad70
  Christudasan Devadasan authored Nov 02, 2022
  a8d7ad70
- [LoongArch] Change the name of LoongArchPreRAExpandPseudo pass · 389cf0ad
  wanglei authored Nov 04, 2022
  389cf0ad
- [IR] Switch everything to use memory attribute · 304f1d59
  Nikita Popov authored Nov 02, 2022
  304f1d59
- [AArch64] SME2 multi-vec unpack, ZIP, frint for two and four registers · 529a932e
  Caroline Concatto authored Nov 02, 2022
  529a932e
- [AArch64][SVE] Extend PTEST_ANY(X=OP(PG,...), X) -> PTEST_ANY(PG, X)) instcombine · 50621169
  Cullen Rhodes authored Nov 04, 2022
  50621169
- [AMDGPU] Create new instructions in SIInstrInfo::moveToVALU · ea60545b
  Jay Foad authored Oct 31, 2022
  ea60545b
- [RISCV] Add FMV_H_X/FMV_W_X/FCVT_H_W/FCVT_H_WU to isAllUsesReadW in SExtWRemoval. · 2fb13247
  Craig Topper authored Nov 03, 2022
  2fb13247
- [RISCV] Change SEXT_B/SEXT_H/ZEXT_H_RV64 handling in isAllUsesReadW in SExtWRemoval. · 4a6ef007
  Craig Topper authored Nov 03, 2022
  4a6ef007
- [X86] Support -march=raptorlake, meteorlake · a806fc27
  Freddy Ye authored Nov 04, 2022
  a806fc27
- [RISCV] Add missing break to the last case in a switch. NFC · 374e6462
  Craig Topper authored Nov 03, 2022
  374e6462
Nov 03, 2022
- [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection. · f62d8a1a
  Mingming Liu authored Nov 02, 2022
  f62d8a1a
- Revert "[AArch64] Improve codegen for shifted mask op" · 74bace2d
  Nathan Chancellor authored Nov 03, 2022
  74bace2d