llvm-svn: 342771

Summary:
This name is more accurate and I want to reuse the simd-conversions
name for testing the actual conversion ops.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52333

llvm-svn: 342761

Currently the code-model does not get saved in the module IR,
so if a code model is specified when compiling with LTO,
it gets lost and is not propagated properly to LTO. This patch,
along with one for the front end, fixes that.

Differential Revision: https://reviews.llvm.org/D52322

llvm-svn: 342760

The code was already using union and memcpy to do this. Remove the memcpy. We can't just change the union because a reference to its member is returned.

llvm-svn: 342759

llvm-svn: 342756

llvm-svn: 342755

Summary:
This ensures we have the non-register version of the instruction.

The stack version of call_indirect now wants a type index argument,
so that has been added in the existing tests.

Tested:
llvm-lit -v `find test -name WebAssembly`

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51662

llvm-svn: 342753

The constant-extender optimization does a form of code motion, which is
complicated in the presence of exception handling.

llvm-svn: 342751

This code:
  bits<96> X = 0;
was triggering undefined behaviour since it iterates over bits 0..95 and tests
them against the IntInit using 1LL << I.

This patch resolves the undefined behaviour by continuing to treat the IntInit
as a 64-bit value and simply causing all bit tests in excess of 64-bits to report
false. As a result,
  bits<96> X = -1;
will be equivalent to:
  bits<96> X;
  let X{0-63} = -1;
  let X{64-95} = 0;

llvm-svn: 342744

"[AMDGPU] lower-switch in preISel as a workaround for legacy DA"

This broke regression tests. The first breakage was noticed here:
http://lab.llvm.org:8011/builders/lld-x86_64-freebsd/builds/23549

llvm-svn: 342743

rdar://44642447

Differential Revision: https://reviews.llvm.org/D52335

llvm-svn: 342742

There are folds under visitExtractElementInst() that don't appear
to have any test coverage, so adding a few basic cases here.

llvm-svn: 342740

Summary: As discussed in r341853 by blaikie, the reinterpret_cast was technically an aliasing violation. Restrict our bit_cast implementation to To which are trivially-constructible (and note the existing restriction to constexpr). Once we move to C++17 we can use a version of bit_cast without these restrictions, or if we care we can SFINAE a different implementation when To isn't trivially-constructible.

Originally landed in r342710 and reverted in r342711 because is_trivially_copyable is only in GCC 5.1 and later.

Reviewers: dblaikie, rsmith

Subscribers: dexonsmith, kristina, llvm-commits

Differential Revision: https://reviews.llvm.org/D52332

llvm-svn: 342739

Summary:
On SNB, renamer-based zeroing does not work for:
 - 16 and 8-bit GPRs[1].
 - MMX [2].
 - ANDN variants [3]

[1] echo 'sub %ax, %ax' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
[2] echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
[3] echo 'andnps %xmm0, %xmm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-

Reviewers: RKSimon, andreadb

Subscribers: gbedwell, craig.topper, llvm-commits

Differential Revision: https://reviews.llvm.org/D52358

llvm-svn: 342736

This patch introduces a SchedWriteVariant to describe zero-idiom VXORP(S|D)Yrr
and VANDNP(S|D)Yrr.

This is a follow-up of r342555.

On Jaguar, a VXORPSYrr is 2 macro opcodes. Only one opcode is eliminated at
register-renaming stage. The other opcode has to be executed to set the upper
half of the destination YMM.
Same for VANDNP(S|D)Yrr.

Differential Revision: https://reviews.llvm.org/D52347

llvm-svn: 342728

Update Assembler/debug-info.ll to contain discriminator.

llvm-svn: 342727

llvm-svn: 342726

https://reviews.llvm.org/D42082 introduced variant parts to debug info
in LLVM. Subsequent work on the Rust compiler has found a bug in that
patch; namely, there is a path in MetadataLoader that fails to restore
the discriminator.

This patch fixes the bug.

Patch by: Tom Tromey

Differential revision: https://reviews.llvm.org/D52340

llvm-svn: 342725

This suppresses CoreFoundation originated leaks in the dsymutil tests.
I'm not sure if this is a false positive or not, but either way we don't
have control over it and shouldn't keep the bot red.

http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan/

llvm-svn: 342724

I'm still not 100% sure that this is not UB lingering (Optional has UB
and should use std::launder, but we don't have std::launder)

llvm-svn: 342723

Summary:
The default target of the switch instruction may sometimes be an
"unreachable" block, when it is guaranteed that one of the cases is
always taken. The dominator tree concludes that such a switch
instruction does not have an immediate post dominator. This confuses
divergence analysis, which is unable to propagate sync dependence to
the targets of the switch instruction.

As a workaround, the AMDGPU target now invokes lower-switch as a
preISel pass. LowerSwitch is designed to handle the unreachable
default target correctly, allowing the divergence analysis to locate
the correct immediate dominator of the now-lowered switch.

Reviewers: arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits, simoll

Differential Revision: https://reviews.llvm.org/D52221

llvm-svn: 342722

    Summary: This change is the first part of the AMDGPU target description
    change. The aim of it is the effective splitting the vector and scalar
    flows at the selection stage. Selection uses predicate functions based
    on the framework implemented earlier - https://reviews.llvm.org/D35267

    Differential revision: https://reviews.llvm.org/D52019

    Reviewers: rampitec

llvm-svn: 342719

This extends the verifier to catch three new errors:

  * Missing DW_AT_type attributes for DW_TAG_formal_parameter,
    DW_TAG_variable and DW_TAG_array_type.

  * Valid references for DW_AT_type pointing to a non-type tag.

Differential revision: https://reviews.llvm.org/D52223

llvm-svn: 342713

Verify that DW_AT_specification and DW_AT_abstract_origin reference a
DIE with a compatible tag.

Differential revision: https://reviews.llvm.org/D38719

llvm-svn: 342712

Of course some bots don't have std::is_trivially_constructible...

llvm-svn: 342711

Summary: As discussed in r341853 by blaikie, the reinterpret_cast was technically an aliasing violation. Restrict our bit_cast implementation to To which are trivially-constructible (and note the existing restriction to constexpr). Once we move to C++17 we can use a version of bit_cast without these restrictions, or if we care we can SFINAE a different implementation when To isn't trivially-constructible.

Reviewers: dblaikie, rsmith

Subscribers: dexonsmith, kristina, llvm-commits

Differential Revision: https://reviews.llvm.org/D52332

llvm-svn: 342710

Summary:
his code was in CGDecl.cpp and really belongs in LLVM's isBytewiseValue. Teach isBytewiseValue the tricks clang's isRepeatedBytePattern had, including merging undef properly, and recursing on more types.

clang part of this patch: D51752

Subscribers: dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51751

llvm-svn: 342709

There is a memory leak which is detected in some of the sanitizer builds.
MCSymbolWasm contains SmallVectors for holding signature information,
however MCContext doesn't run destructors for MCSymbols, so in cases
where the SmallVectors heap-allocate, the memory is leaked.

llvm-svn: 342707

Summary:
There isn't any actual dependency - there's one #include from CodeGen
but nothing from the header is actually used.

With this change we can use the MCA library from CodeGen without
circular dependencies (e.g. for scheduling).

Reviewers: andreadb

Reviewed By: andreadb

Authored By: orodley

Subscribers: mgorny, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D52288

llvm-svn: 342706

In my original diff I missed #include "llvm/System/Thing.h" and forgot to update a
reference to .inc files a few lines down. This patch corrects these things as 
they were missed in revision 342500.

llvm-svn: 342705

This is a bit easier to follow than handling the copy and src maps
directly in the pass, and will make upcoming changes to how this is
done easier to follow.

llvm-svn: 342703

Summary:
Implement --version for objcopy and strip.

I think there are LLVM utilities that automatically handle this, but that doesn't seem to work with custom parsing since this binary handles both objcopy and strip, so it uses custom parsing.

This fixes PR38298

Reviewers: jhenderson, alexshap, jakehehrlich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52328

llvm-svn: 342702

This makes WebAssembly build by default, rather than requiring
LLVM_EXPERIMENTAL_TARGETS_TO_BUILD!

Differential Revision: https://reviews.llvm.org/D43211

llvm-svn: 342701

llvm-svn: 342700

Fix DenseSet::ConstIterator pointer/reference typedefs to be const

Patch by Brad Moody!

Differential Revision: https://reviews.llvm.org/D52260

llvm-svn: 342697

https://reviews.llvm.org/D52127

This patch adds the ability to watch for insertions/deletions of
MachineInstructions similar to MachineRegisterInfo.

llvm-svn: 342696

llvm-svn: 342694

Currently, BPF has XADD (locked add) insn support and the
asm looks like:
  lock *(u32 *)(r1 + 0) += r2
  lock *(u64 *)(r1 + 0) += r2
The instruction itself does not have a return value.

At the source code level, users often use
  __sync_fetch_and_add()
which eventually translates to XADD. The return value of
__sync_fetch_and_add() is supposed to be the old value
in the xadd memory location. Since BPF::XADD insn does not
support such a return value, this patch added a PreEmit
phase to check such a usage. If such an illegal usage
pattern is detected, a fatal error will be reported like
  line 4: Invalid usage of the XADD return value
if compiled with -g, or
  Invalid usage of the XADD return value
if compiled without -g.

Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 342692

Summary: Depends on D52105.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52254

llvm-svn: 342691

Summary: Adds the necessary support to lib/ObjectYAML and fixes SIMD
calls to allow the tests to work. Also removes some dead code that
would otherwise have to have been updated.

Reviewers: aheejin, dschuff, sbc100

Subscribers: jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52105

llvm-svn: 342689