This is necessary, but not sufficient, for having working SJLJ exception
handling on x86_64.

Differential Revision: https://reviews.llvm.org/D38254

llvm-svn: 314277

The callsite value is already stored indexed from 0 in
the _Unwind_Context struct. When accessed via the functions
_Unwind_GetIP and _Unwind_SetIP, the value is indexed from 1,
but those functions handle the offseting. When reading directly
from the struct here, we shouldn't subtract 1.

This matches the code generated by the ARM target, where SJLJ
exception handling is used by default on iOS.

This makes clang-built object files for 32 bit x86 mingw work when
linked with libgcc/libstdc++.

Differential Revision: https://reviews.llvm.org/D38251

llvm-svn: 314276

This matches the types of the struct members defined in
lib/CodeGen/SjLjEHPrepare.cpp, and the definition of this struct in libgcc.

Differential Revision: https://reviews.llvm.org/D38248

llvm-svn: 314275

llvm-svn: 314274

MemorySSAUpdater: Only add phis to insertedphis if we actually inserted them, not if we just found existing ones

llvm-svn: 314273

Some of the operations are being sign extended to 512 bits with avx512bw.

llvm-svn: 314272

[SelectionDAG] Make NewSDValueDbgMsg print target specific nodes correctly by passing in the SelectionDAG.

llvm-svn: 314271

Followup to D32840.

llvm-svn: 314270

Summary:
A new FDR metadata record will support logging a function call argument;
appending multiple metadata records will represent a sequence of arguments
meaning that "holes" are not representable by the buffer format.  Each
call argument is currently a 64-bit value (useful for "this" pointers and
synchronization objects).

If present, we put this argument to the function call "entry" record it
belongs to, and alter its type to notify the user of its presence.

Reviewers: dberris

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32840

llvm-svn: 314269

llvm-svn: 314268

llvm-svn: 314267

This patch tries to transform cases like:

for (unsigned i = 0; i < N; i += 2) {
  bool c0 = (i & 0x1) == 0;
  bool c1 = ((i + 1) & 0x1) == 1;
}
To

for (unsigned i = 0; i < N; i += 2) {
  bool c0 = true;
  bool c1 = true;
}

This commit also update test/Transforms/IndVarSimplify/replace-srem-by-urem.ll to prevent constant folding.

Differential Revision: https://reviews.llvm.org/D38272

llvm-svn: 314266

stack pointer for apple's armv7 ABI.  When in a frameless function
or in a prologue/epilogue where sp wasn't properly aligned, we could
try to make function calls with an unaligned sp; the expression
would crash.

llvm-svn: 314265

Keep space before or after the &/&& tokens, but not both. For example,
  auto [x,y] = a;
  auto &[xr, yr] = a; // LLVM style
  auto& [xr, yr] = a; // google style

Differential Revision:https://reviews.llvm.org/D35743

llvm-svn: 314264

This change adds support for dynamic relocations (allocated
SHT_REL/SHT_RELA sections with a dynamic symbol table as their link).

I had to reland this because of a I wasn't initilizing some pointers.

llvm-svn: 314263

Currently, if _attribute_((section())) is used for extern variables, 
section information is not emitted in generated IR when the variables are used. 
This is expected since sections are not generated for external linkage objects. 
However NiosII requires this information as it uses special GP-relative accesses 
for any objects that use attribute section (.sdata). GCC keeps this attribute in 
  middle-end.

This change emits the section information for all targets.

Patch By: Elizabeth Andrews

Differential Revision:https://reviews.llvm.org/D36487

llvm-svn: 314262

Broken since r314111

V2: pointed out by Jan Vesely
   - Use format() instead of % formating

Patch-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 314261

llvm-svn: 314259

llvm-svn: 314258

This warning "structure was padded due to alignment specifier" says
that the compiler is going to do exactly what you asked it to do.
It's triggered by the tests for over-aligned dynamic memory allocation.

llvm-svn: 314257

In r314227, it wasn't always, and would thus contain random garbage.

llvm-svn: 314256

Summary:
Align __aeabi_memclr to 4 bytes. All other ARM functions are already aligned to
4-bytes in compiler-rt.
(Split off from review D38227)

Reviewers: compnerd, peter.smith, srhines, weimingz, rengolin, kristof.beyls

Reviewed By: compnerd

Subscribers: aemerson, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D38271

llvm-svn: 314255

This patch makes DeleteEdge correctly invalidate DFS numbers in the
incremental updater. This should fix PR34466 and related bugs.

llvm-svn: 314254

Summary:
Don't bail out on constant divisors for divisions that can be narrowed without
introducing control flow .  This gives us a 32 bit multiply instead of an
emulated 64 bit multiply in the generated PTX assembly.

Reviewers: jlebar

Subscribers: jholewinski, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D38265

llvm-svn: 314253

Summary:
In rare cases, loads that don't get prefetched that were marked as
strided loads could cause a crash if they occurred in a loop with other
colliding loads.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38261

llvm-svn: 314252

[AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations.

Summary:
This addresses a correctness bug for LD[1234]*_POST opcodes that have
the prefetcher fix applied to them: the base register was not being
written back from the temp after being incremented, so it would appear
to never be incremented.

Also, fix some opcode tag computations based on some updated HW details
to get better tag avoidance and thus better prefetcher performance.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38256

llvm-svn: 314251

llvm-svn: 314250

Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.""

The late MOV8rr_NOREX that caused the crash has been removed.

llvm-svn: 314249

This hook is called after register allocation with two physical registers. We don't need a separate instruction at that time to force register class constraints. I left in the assert though. We also have a fatal error in X86MCCodeEmitter if we ever encode an H-reg and a REX prefix.

llvm-svn: 314248

llvm-svn: 314247

llvm-svn: 314246

Previously these were being included as both imports and
exports, with the import being satisfied by the export
(or some strong symbol) at runtime.  However proved
unnecessary and actually complicated linking as it meant
there was not a 1-to-1 mapping between a wasm function
/global index and a linker symbol.

Differential Revision: https://reviews.llvm.org/D38246

llvm-svn: 314245

In the past while, I've committed a number of patches in the PowerPC back end
aimed at eliminating comparison instructions. However, this causes some failures
in proprietary source and these issues are not observed in SPEC or any open
source packages I've been able to run.
As a result, I'm pulling the entire series and will refactor it to:
- Have a single entry point for easy control
- Have fine-grained control over which patterns we transform

A side-effect of this is that test cases for these patches (and modified by
them) are XFAIL-ed. This is a temporary measure as it is counter-productive
to remove/modify these test cases and then have to modify them again when
the refactored patch is recommitted.
The failure will be investigated in parallel to the refactoring effort and
the recommit will either have a fix for it or will leave this transformation
off by default until the problem is resolved.

llvm-svn: 314244

llvm-svn: 314243

Add padding inside team structure to keep same structure size.

llvm-svn: 314242

This function is used to perform semantic analysis on Microsoft style
`__va_start`.  Rename it to make this more explicit.  `__va_start` is
marked as `ALL_MS_LANGUAGES`, and requires Microsoft compatibility.
Other GNU targets will use `__builtin_va_start` instead.  NFC.

Addresses post-commit review comments from David Majnemer.

llvm-svn: 314241

llvm-svn: 314240

Add support for the `preserve_mostcc` and `preserve_allcc` on Windows
x86_64 and AArch64.  This is used by Swift.

llvm-svn: 314236

It was brought up in response to my last implementation for
this struct-as-interface features that at least 1 header in
the MS SDK uses "extern C++" around an IUnknown declaration.

The previous implementation demanded that this type exist
in the TranslationUnit DeclContext.  This small change simply
also allows in the situation where we're extern "C++".

llvm-svn: 314235

[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF{8|16|32} stride 3)

This patch expands the support of lowerInterleavedStore to {8|16|32}x8i stride 3.

LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) .
This patch is part two of two patches and it covers the store (interlevaed) side.

The patch goal is to optimize the following sequence:
a0 a1 a2 a3 a4 a5 a6 a7
b0 b1 b2 b3 b4 b5 b6 b7
c0 c1 c2 c3 c4 c5 c6 c7

into
a0 b0 c0 a1 b1 c1 a2 b2
c2 a3 b3 c3 a4 b4 c4 a5
b5 c5 a6 b6 c6 a7 b7 c7

Reviewers:
zvi
guyblank
dorit
Ayal

Differential Revision: https://reviews.llvm.org/D37117

Change-Id: I56ced8bcbea809a37654060771911ade20246ccc
llvm-svn: 314234