Commits · ad1f5457d2d89efa49a722404a5f0b744b7a64d1 · Roger Ferrer / llvm-epi · GitLab

Jul 16, 2021
- [RISCV] Teach constant materialization that it can use zext.w at the end with... · 4dbb7880
  Craig Topper authored Jul 16, 2021
  4dbb7880
Jun 18, 2021
- RISCV: simplify a test case for RISCV (NFCI) · b30bc8cc
  Saleem Abdulrasool authored Jun 18, 2021
  b30bc8cc
Jun 17, 2021
- RISCV: clean up target expression handling · 116841c6
  Saleem Abdulrasool authored Jun 17, 2021
  116841c6
- RISCV: adjust handling of relocation emission for RISCV · bbea6425
  Saleem Abdulrasool authored May 26, 2021
  bbea6425
Jun 09, 2021
- [RISCV] Fix failing RVV MC tests · 292f4197
  Fraser Cormack authored Jun 09, 2021
  292f4197
May 29, 2021
- Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" · 00dfd4f8
  Jessica Clarke authored May 29, 2021
  00dfd4f8
- [RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases · aa9a30b8
  Jessica Clarke authored May 29, 2021
  aa9a30b8
May 26, 2021
- [RISCV][NFC] Fix some whitespace nits in MC test RUN lines · e4fc8c3d
  Jessica Clarke authored May 26, 2021
  
  e4fc8c3d
- [llvm-mc] Add -M to replace -riscv-no-aliases and -riscv-arch-reg-names · 73a11795
  Fangrui Song authored May 26, 2021
  73a11795
May 21, 2021
- RISCV: add a few deprecated aliases for CSRs · 6c6b3e3a
  Saleem Abdulrasool authored May 05, 2021
  6c6b3e3a
May 04, 2021
- [MC] Remove unneeded "in '.xxx' directive" from diagnostics · 3d473ae7
  Fangrui Song authored May 04, 2021
  3d473ae7
- [RISCV][test] Migrate llvm-objdump --riscv-no-aliases to -M no-aliases · 1a79381b
  Fangrui Song authored May 04, 2021
  1a79381b
Apr 23, 2021
- [RISCV] Have assembler check that the temp register is different than dest... · fae1d31c
  Craig Topper authored Apr 23, 2021
  fae1d31c
- [RISCV] [1/2] Add IR intrinsic for Zbp extension · b49337bb
  Levy Hsu authored Apr 22, 2021
  b49337bb
Apr 21, 2021
- [RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0. · a8822caa
  Craig Topper authored Apr 21, 2021
  a8822caa
- [RISCV][MC] Mask load should not have VMConstraint. · ad0fe5db
  Zakk Chen authored Apr 08, 2021
  ad0fe5db
Apr 14, 2021
- Title: [RISCV] Add missing part of instruction vmsge {u}. VX Review By:... · 645ce31c
  root authored Apr 14, 2021
  645ce31c
Apr 09, 2021
- [RISCV][NFC] Fix formatting · 6169f153
  Jim Lin authored Apr 09, 2021
  
  6169f153
Apr 08, 2021
- [RISCV] Add InstAlias for Zbb Zbp and Zbs extension · 461b5549
  Levy Hsu authored Apr 08, 2021
  461b5549
Apr 02, 2021
- [RISCV] Improve 64-bit integer constant materialization for more cases. · d7ffa82a
  Craig Topper authored Apr 02, 2021
  d7ffa82a
- [RISCV] Add missing CHECK-EXPAND line to one case in rv64i-aliases-valid.s. · f6790bec
  Craig Topper authored Apr 02, 2021
  f6790bec
Apr 01, 2021
- [RISCV] Improve 64-bit integer materialization for some cases. · d61b40ed
  Craig Topper authored Apr 01, 2021
  d61b40ed
Mar 28, 2021
- [RISCV] Add vfabs.v pseudo instruction. · bc82e9bf
  Hsiangkai Wang authored Mar 27, 2021
  bc82e9bf
Mar 09, 2021
- [RISCV][MC] Fix nf encoding for vector ld/st whole register · 5cdb2e98
  ShihPo Hung authored Mar 08, 2021
  5cdb2e98
Mar 06, 2021
- [MC][RISCV] Support .reloc *, BFD_RELOC_{NONE,32,64}, * · 2d922de3
  Fangrui Song authored Mar 05, 2021
  2d922de3
Feb 23, 2021
- [RISCV] vle1.v/vse1.v should be unmasked instructions. · 53c4c2b9
  Hsiangkai Wang authored Feb 23, 2021
  53c4c2b9
Feb 12, 2021
- [RISCV] Change parseVTypeI function · feaf1d81
  luxufan authored Feb 12, 2021
  feaf1d81
Feb 09, 2021
- [RISCV] Remove SRO* and SLO* instructions from bitmanip. · fd5adae0
  Craig Topper authored Feb 09, 2021
  fd5adae0
- [RISCV] Use whole register load/store for generic load/store. · a2d19bad
  Hsiangkai Wang authored Feb 09, 2021
  a2d19bad
Feb 03, 2021
- [RISCV] Add new vector instructions in v0.10. · c7189ba7
  Hsiangkai Wang authored Feb 01, 2021
  c7189ba7
Jan 30, 2021
- [RISCV] Update the version number to v0.10 for vector. · 282aca10
  Hsiangkai Wang authored Jan 29, 2021
  282aca10
Jan 27, 2021
- [RISCV] Add rv64 run lines to rv32 MC layer tests for B extension · e1d61789
  Craig Topper authored Jan 26, 2021
  e1d61789
Jan 26, 2021
- [RISCV] Update V extension to v1.0-draft 08a0b464. · f19849a0
  Hsiangkai Wang authored Jan 13, 2021
  f19849a0
Jan 25, 2021
- [RISCV] Add attribute support for all supported extensions · a7c1239f
  Simon Cook authored Jan 25, 2021
  a7c1239f
Jan 22, 2021
- [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32. · 607e5a50
  Craig Topper authored Jan 22, 2021
  607e5a50
- [RISCV] Add xperm.* instructions to Zbp extension. · f25f7e8e
  Craig Topper authored Jan 22, 2021
  f25f7e8e
- [RISCV] Add support for rev8 and orc.b to Zbb. · 4d5aa760
  Craig Topper authored Jan 22, 2021
  4d5aa760
- [RISCV] Add zext.h instruction to Zbb. · 3c94cee6
  Craig Topper authored Jan 22, 2021
  3c94cee6
- [RISCV] Move pack instructions to Zbp extension only. · 83c92fde
  Craig Topper authored Jan 22, 2021
  83c92fde
- [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack. · 5ae92f1e
  Craig Topper authored Jan 22, 2021
  5ae92f1e