Commits · b006dafbef716d4392d52fd35879112ce2fb4d91 · Roger Ferrer / llvm-epi · GitLab

Aug 02, 2018
- [PowerPC] Do not round values prior to converting to integer · e1a525ed
  Nemanja Ivanovic authored Aug 02, 2018
  e1a525ed
Aug 01, 2018
- [SelectionDAG] fix bug in translating funnel shift with non-power-of-2 type · 8aac22e0
  Sanjay Patel authored Aug 01, 2018
  8aac22e0
Jul 31, 2018
- [DAGCombiner] transform sub-of-shifted-signbit to add · 9f807f44
  Sanjay Patel authored Jul 30, 2018
  9f807f44
Jul 27, 2018
- [AArch64, PowerPC, x86] add more signbit math tests; NFC · 06c7d5ae
  Sanjay Patel authored Jul 27, 2018
  06c7d5ae
- [AArch64, PowerPC, x86] add more signbit math tests; NFC · efac39ee
  Sanjay Patel authored Jul 27, 2018
  efac39ee
- [DAGCombiner] fold 'not' with signbit math · c7abb416
  Sanjay Patel authored Jul 27, 2018
  c7abb416
- [PowerPC] add more tests for signbit math; NFC · 60c04b96
  Sanjay Patel authored Jul 27, 2018
  60c04b96
Jul 25, 2018
- [SelectionDAG] try to convert funnel shift directly to rotate if legal · 215dcbf4
  Sanjay Patel authored Jul 25, 2018
  215dcbf4
- [AArch, PowerPC] add more tests for legal rotate ops; NFC · f94c4c84
  Sanjay Patel authored Jul 25, 2018
  f94c4c84
Jul 19, 2018
- [Power9] Code Cleanup - Remove needsAggressiveScheduling() · 0c122d5a
  Stefan Pintilie authored Jul 19, 2018
  0c122d5a
Jul 18, 2018
- Introduce codegen for the Signal Processing Engine · d52990c7
  Justin Hibbits authored Jul 18, 2018
  d52990c7
Jul 17, 2018
- [Intrinsics] define funnel shift IR intrinsics + DAG builder support · c71adc80
  Sanjay Patel authored Jul 16, 2018
  c71adc80
Jul 15, 2018
- [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) · a41c886c
  Sanjay Patel authored Jul 15, 2018
  a41c886c
Jul 13, 2018
- [PowerPC] Materialize more constants with CR-field set in late peephole · 080c3505
  Nemanja Ivanovic authored Jul 13, 2018
  080c3505
Jul 12, 2018
- [PowerPC] [NFC] Update __float128 tests · 94259ba1
  Stefan Pintilie authored Jul 12, 2018
  94259ba1
Jul 11, 2018
- [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests · 9fa9c936
  Joel E. Denny authored Jul 11, 2018
  9fa9c936
- [Power9] Add remaining __flaot128 builtin support for FMA round to odd · b9d01aa2
  Stefan Pintilie authored Jul 11, 2018
  b9d01aa2
Jul 09, 2018
- [Power9] Add __float128 builtins for Rounding Operations · 133acb22
  Stefan Pintilie authored Jul 09, 2018
  133acb22
- [Power9] [LLVM] Add __float128 support for trunc to double round to odd · 58e3e0a8
  Stefan Pintilie authored Jul 09, 2018
  58e3e0a8
- [Power9] Add __float128 builtins for Round To Odd · 83a5fe14
  Stefan Pintilie authored Jul 09, 2018
  83a5fe14
- [Power9] Add __float128 support for compare operations · 3d76326d
  Stefan Pintilie authored Jul 09, 2018
  3d76326d
Jul 06, 2018
- [Power9] Add __float128 library call for frem · b351f09c
  Stefan Pintilie authored Jul 06, 2018
  b351f09c
Jul 05, 2018
- [Power9] Add lib calls for float128 operations with no equivalent PPC instructions · 5612b906
  Lei Huang authored Jul 05, 2018
  5612b906
- [AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC · bce899ff
  Sanjay Patel authored Jul 05, 2018
  bce899ff
- [Power9] Optimize codgen for conversions of int to float128 · 66e22c21
  Lei Huang authored Jul 05, 2018
  66e22c21
- [Power9][NFC] add back-end tests for passing homogeneous fp128 aggregates by value · 9d70afbb
  Lei Huang authored Jul 05, 2018
  9d70afbb
- [Power9] Add tests for passing float128 in VSX reg for non-homogenous aggregates · 5bab646c
  Lei Huang authored Jul 05, 2018
  5bab646c
- [Power9]Legalize and emit code for quad-precision convert from single-precision · d17c39cc
  Lei Huang authored Jul 05, 2018
  d17c39cc
- [Power9] Implement float128 parameter passing and return values · a26f3be4
  Lei Huang authored Jul 05, 2018
  a26f3be4
Jul 04, 2018
- [Power9]Legalize and emit code for round & convert quad-precision values · 6270ab6c
  Lei Huang authored Jul 04, 2018
  6270ab6c
- [PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler · cb4f0c5c
  Stefan Pintilie authored Jul 04, 2018
  cb4f0c5c
- NFC - Various typo fixes in tests · da4a966e
  Gabor Buella authored Jul 04, 2018
  da4a966e
Jul 02, 2018
- [PowerPC] Don't make it as pre-inc candidate if displacement isn't 4's... · 3b2aa2b4
  QingShan Zhang authored Jul 02, 2018
  3b2aa2b4
Jun 27, 2018
- [DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros · d052de85
  Sanjay Patel authored Jun 27, 2018
  d052de85
Jun 24, 2018
- [DAGCombiner] eliminate setcc bool math when input is low-bit of some value · 962ee178
  Sanjay Patel authored Jun 24, 2018
  962ee178
Jun 23, 2018
- [PowerPC] add more tests for bit hacking opportunities with setcc; NFC · 0fe8ea56
  Sanjay Patel authored Jun 22, 2018
  0fe8ea56
Jun 22, 2018
- [PowerPC] add tests for bit hacking opportunities with setcc; NFC · 6e505e43
  Sanjay Patel authored Jun 22, 2018
  6e505e43
Jun 21, 2018
- [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property · 42f7bc96
  Mikael Holmen authored Jun 21, 2018
  42f7bc96
- Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred. · dfd14ade
  Alina Sbirlea authored Jun 20, 2018
  dfd14ade
Jun 20, 2018
- Allow binop C1, (select cc, CF, CT) -> select folding · 20279dc0
  Stanislav Mekhanoshin authored Jun 20, 2018
  20279dc0